| Message ID | c35dca71-fc63-7628-d483-ad690bea7ced@cogentembedded.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Sergei, On Fri, Feb 2, 2018 at 7:46 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the R8A77980 SoC based Condor board. > The board has 1 debug serial port (SCIF0); include support for it, so > that the serial console can work. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Thanks for your patch! > --- /dev/null > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the Condor board > + * > + * Copyright (C) 2018 Renesas Electronics Corp. > + * Copyright (C) 2018 Cogent Embedded, Inc. > + */ > + > +/dts-v1/; > +#include "r8a77980.dtsi" > + > +/ { > + model = "Renesas Condor board based on r8a77980"; > + compatible = "renesas,condor", "renesas,r8a77980"; > + > + aliases { > + serial0 = &scif0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x38000000>; According to the Samsung website, the LPDDR is a 16 Gib part, i.e. 2 GiB. Is there any specific reason you're limiting memory to 1 GiB? > + }; With the above resolved: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Index: renesas/arch/arm64/boot/dts/renesas/Makefile =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/Makefile +++ renesas/arch/arm64/boot/dts/renesas/Makefile @@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-sa dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas Condor board based on r8a77980"; + compatible = "renesas,condor", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +};