diff mbox

[06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

Message ID 1517921899-25926-7-git-send-email-vidya.srinivas@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Srinivas, Vidya Feb. 6, 2018, 12:58 p.m. UTC
From: Mahesh Kumar <mahesh1.kumar@intel.com>

This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

Comments

Sharma, Shashank Feb. 7, 2018, 4:46 p.m. UTC | #1
Regards

Shashank


On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This will reduce number of arguments required to be passed in
> skl_compute_plane_wm function.
The commit message can be like "This patch is passes skl_wm_level 
structure itself to watermark computation function (instead of its 
internal parameters). It reduces number of arguments required to be passed"
With or without this change,
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
>   1 file changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b3d1bf7..07fc084 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4531,9 +4531,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   				uint16_t ddb_allocation,
>   				int level,
>   				const struct skl_wm_params *wp,
> -				uint16_t *out_blocks, /* out */
> -				uint8_t *out_lines, /* out */
> -				bool *enabled /* out */)
> +				struct skl_wm_level *result /* out */)
>   {
>   	const struct drm_plane_state *pstate = &intel_pstate->base;
>   	uint32_t latency = dev_priv->wm.skl_latency[level];
> @@ -4547,7 +4545,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   
>   	if (latency == 0 ||
>   	    !intel_wm_plane_visible(cstate, intel_pstate)) {
> -		*enabled = false;
> +		result->plane_en = false;
>   		return 0;
>   	}
>   
> @@ -4627,7 +4625,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   
>   	if (res_blocks >= ddb_allocation || res_lines > 31 ||
>   	    min_disp_buf_needed >= ddb_allocation) {
> -		*enabled = false;
> +		result->plane_en = false;
>   
>   		/*
>   		 * If there are no valid level 0 watermarks, then we can't
> @@ -4646,9 +4644,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   		}
>   	}
>   
> -	*out_blocks = res_blocks;
> -	*out_lines = res_lines;
> -	*enabled = true;
> +	result->plane_res_b = res_blocks;
> +	result->plane_res_l = res_lines;
> +	result->plane_en = true;
>   
>   	return 0;
>   }
> @@ -4689,9 +4687,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>   					   ddb_blocks,
>   					   level,
>   					   wm_params,
> -					   &result->plane_res_b,
> -					   &result->plane_res_l,
> -					   &result->plane_en);
> +					   result);
>   		if (ret)
>   			return ret;
>   	}
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3d1bf7..07fc084 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,9 +4531,7 @@  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
-				uint16_t *out_blocks, /* out */
-				uint8_t *out_lines, /* out */
-				bool *enabled /* out */)
+				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4547,7 +4545,7 @@  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	if (latency == 0 ||
 	    !intel_wm_plane_visible(cstate, intel_pstate)) {
-		*enabled = false;
+		result->plane_en = false;
 		return 0;
 	}
 
@@ -4627,7 +4625,7 @@  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	if (res_blocks >= ddb_allocation || res_lines > 31 ||
 	    min_disp_buf_needed >= ddb_allocation) {
-		*enabled = false;
+		result->plane_en = false;
 
 		/*
 		 * If there are no valid level 0 watermarks, then we can't
@@ -4646,9 +4644,9 @@  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
-	*out_blocks = res_blocks;
-	*out_lines = res_lines;
-	*enabled = true;
+	result->plane_res_b = res_blocks;
+	result->plane_res_l = res_lines;
+	result->plane_en = true;
 
 	return 0;
 }
@@ -4689,9 +4687,7 @@  skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
-					   &result->plane_res_b,
-					   &result->plane_res_l,
-					   &result->plane_en);
+					   result);
 		if (ret)
 			return ret;
 	}