| Message ID | 1517921899-25926-11-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: > From: Chandra Konduru <chandra.konduru@intel.com> > > This patch sets appropriate scaler mode for NV12 format. > In this mode, skylake scaler does either chroma-upsampling or > chroma-upsampling and resolution scaling > > v2: Review comments from Ville addressed > NV12 case to be checked first for setting > the scaler > > v3: Rebased (me) > > v4: Rebased (me) > > v5: Missed the Tested-by/Reviewed-by in the previous series > Adding the same to commit message in this version. > > v6: Rebased (me) > > v7: Rebased (me) > > v8: Rebased (me) > Restricting the NV12 change for scaler to BXT and KBL > in this series. > > v9: Rebased (me) > > v10: As of now, NV12 has been tested on Gen9 and Gen10. However, > code is applicable to all GEN >= 9. Hence making > that change to keep it generic. I am not sure if the same code is applicable for all GEN > 9, I am seeing a different bit definition for GEN > 10 for bit 29:28 > Comments under v8 is not valid anymore. > > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e9c79b5..18be7be 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6705,6 +6705,7 @@ enum { > #define PS_SCALER_MODE_MASK (3 << 28) > #define PS_SCALER_MODE_DYN (0 << 28) > #define PS_SCALER_MODE_HQ (1 << 28) > +#define PS_SCALER_MODE_NV12 (2 << 28) > #define PS_PLANE_SEL_MASK (7 << 25) > #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) > #define PS_FILTER_MASK (3 << 23) > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c > index d452c32..196427a 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, > } > > /* set scaler mode */ > - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { > - scaler_state->scalers[*scaler_id].mode = 0; > + if ((INTEL_GEN(dev_priv) >= 9) && Same here, this might not be applicable for (GEN > 10) due to different bit definition of 29:28. > + plane_state && plane_state->base.fb && > + plane_state->base.fb->format->format == > + DRM_FORMAT_NV12) { Above alignment should be aligned to first line (INTEL_GEN()) > + scaler_state->scalers[*scaler_id].mode = > + PS_SCALER_MODE_NV12; > } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { > /* > * when only 1 scaler is in use on either pipe A or B,
> -----Original Message----- > From: Sharma, Shashank > Sent: Thursday, February 8, 2018 2:35 PM > To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil > <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>; > Konduru, Chandra <chandra.konduru@intel.com>; Maiti, Nabendu Bikash > <nabendu.bikash.maiti@intel.com> > Subject: Re: [PATCH 10/16] drm/i915: Set scaler mode for NV12 > > Regards > > Shashank > > > On 2/6/2018 6:28 PM, Vidya Srinivas wrote: > > From: Chandra Konduru <chandra.konduru@intel.com> > > > > This patch sets appropriate scaler mode for NV12 format. > > In this mode, skylake scaler does either chroma-upsampling or > > chroma-upsampling and resolution scaling > > > > v2: Review comments from Ville addressed > > NV12 case to be checked first for setting the scaler > > > > v3: Rebased (me) > > > > v4: Rebased (me) > > > > v5: Missed the Tested-by/Reviewed-by in the previous series Adding the > > same to commit message in this version. > > > > v6: Rebased (me) > > > > v7: Rebased (me) > > > > v8: Rebased (me) > > Restricting the NV12 change for scaler to BXT and KBL in this series. > > > > v9: Rebased (me) > > > > v10: As of now, NV12 has been tested on Gen9 and Gen10. However, code > > is applicable to all GEN >= 9. Hence making that change to keep it > > generic. > I am not sure if the same code is applicable for all GEN > 9, I am seeing a > different bit definition for GEN > 10 for bit 29:28 > > Comments under v8 is not valid anymore. > > > > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> > > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> > > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> > > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> > > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++-- > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index e9c79b5..18be7be 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6705,6 +6705,7 @@ enum { > > #define PS_SCALER_MODE_MASK (3 << 28) > > #define PS_SCALER_MODE_DYN (0 << 28) > > #define PS_SCALER_MODE_HQ (1 << 28) > > +#define PS_SCALER_MODE_NV12 (2 << 28) > > #define PS_PLANE_SEL_MASK (7 << 25) > > #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) > > #define PS_FILTER_MASK (3 << 23) > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c > > b/drivers/gpu/drm/i915/intel_atomic.c > > index d452c32..196427a 100644 > > --- a/drivers/gpu/drm/i915/intel_atomic.c > > +++ b/drivers/gpu/drm/i915/intel_atomic.c > > @@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct > drm_i915_private *dev_priv, > > } > > > > /* set scaler mode */ > > - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) > { > > - scaler_state->scalers[*scaler_id].mode = 0; > > + if ((INTEL_GEN(dev_priv) >= 9) && > Same here, this might not be applicable for (GEN > 10) due to different bit > definition of 29:28. Thank u. Will recheck and limit to Gen 9 and 10. > > + plane_state && plane_state->base.fb && > > + plane_state->base.fb->format->format == > > + DRM_FORMAT_NV12) { > Above alignment should be aligned to first line (INTEL_GEN()) > > + scaler_state->scalers[*scaler_id].mode = > > + PS_SCALER_MODE_NV12; > > } else if (num_scalers_need == 1 && intel_crtc->pipe != > PIPE_C) { > > /* > > * when only 1 scaler is in use on either pipe A or B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e9c79b5..18be7be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6705,6 +6705,7 @@ enum { #define PS_SCALER_MODE_MASK (3 << 28) #define PS_SCALER_MODE_DYN (0 << 28) #define PS_SCALER_MODE_HQ (1 << 28) +#define PS_SCALER_MODE_NV12 (2 << 28) #define PS_PLANE_SEL_MASK (7 << 25) #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) #define PS_FILTER_MASK (3 << 23) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index d452c32..196427a 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, } /* set scaler mode */ - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { - scaler_state->scalers[*scaler_id].mode = 0; + if ((INTEL_GEN(dev_priv) >= 9) && + plane_state && plane_state->base.fb && + plane_state->base.fb->format->format == + DRM_FORMAT_NV12) { + scaler_state->scalers[*scaler_id].mode = + PS_SCALER_MODE_NV12; } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { /* * when only 1 scaler is in use on either pipe A or B,