@@ -40,7 +40,7 @@ static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ const struct intel_device_static_info *info = DEVICE_INFO(dev_priv);
struct drm_printer p = drm_seq_file_printer(m);
seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
@@ -507,7 +507,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
seq_printf(m, "%llu [%pa] gtt total\n",
ggtt->base.total, &ggtt->mappable_end);
seq_printf(m, "Supported page sizes: %s\n",
- stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
+ stringify_page_sizes(DEVICE_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
seq_putc(m, '\n');
@@ -3146,7 +3146,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
seq_printf(m, "Global active requests: %d\n",
dev_priv->gt.active_requests);
seq_printf(m, "CS timestamp frequency: %u kHz\n",
- dev_priv->info.cs_timestamp_frequency_khz);
+ DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz);
p = drm_seq_file_printer(m);
for_each_engine(engine, dev_priv, id)
@@ -4012,7 +4012,7 @@ i915_ring_test_irq_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- val &= INTEL_INFO(i915)->ring_mask;
+ val &= DEVICE_INFO(i915)->ring_mask;
DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
@@ -4294,7 +4294,7 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
- const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ const struct intel_device_static_info *info = DEVICE_INFO(dev_priv);
int s_max = 6, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
@@ -4383,7 +4383,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
- INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ DEVICE_INFO(dev_priv)->sseu.subslice_mask;
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4415,16 +4415,16 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ sseu->subslice_mask = DEVICE_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
- INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+ DEVICE_INFO(dev_priv)->sseu.eu_per_subslice;
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
u8 subslice_7eu =
- INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
+ DEVICE_INFO(dev_priv)->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4476,7 +4476,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &DEVICE_INFO(dev_priv)->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
@@ -165,7 +165,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
* (which really amounts to a PCH but no South Display).
*/
- if (INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (DEVICE_INFO(dev_priv)->num_pipes == 0) {
dev_priv->pch_type = PCH_NOP;
return;
}
@@ -344,12 +344,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(&DEVICE_INFO(dev_priv)->sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = INTEL_INFO(dev_priv)->sseu.eu_total;
+ value = DEVICE_INFO(dev_priv)->sseu.eu_total;
if (!value)
return -ENODEV;
break;
@@ -366,7 +366,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = DEVICE_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
intel_runtime_pm_get(dev_priv);
@@ -408,7 +408,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
- * INTEL_INFO(), a feature macro, or similar.
+ * DEVICE_INFO(), a feature macro, or similar.
*/
value = 1;
break;
@@ -416,17 +416,17 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = INTEL_INFO(dev_priv)->sseu.slice_mask;
+ value = DEVICE_INFO(dev_priv)->sseu.slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ value = DEVICE_INFO(dev_priv)->sseu.subslice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
- value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
+ value = 1000 * DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz;
break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
@@ -692,7 +692,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_setup_overlay(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (DEVICE_INFO(dev_priv)->num_pipes == 0)
return 0;
ret = intel_fbdev_init(dev);
@@ -884,9 +884,9 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
static int i915_driver_init_early(struct drm_i915_private *dev_priv,
const struct pci_device_id *ent)
{
- const struct intel_device_info *match_info =
- (struct intel_device_info *)ent->driver_data;
- struct intel_device_info *device_info;
+ const struct intel_device_static_info *match_info =
+ (const struct intel_device_static_info *)ent->driver_data;
+ struct intel_device_static_info *device_info;
int ret = 0;
if (i915_inject_load_failure())
@@ -1242,7 +1242,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (DEVICE_INFO(dev_priv)->num_pipes) {
/* Must be done after probing outputs */
intel_opregion_register(dev_priv);
acpi_video_register();
@@ -1266,7 +1266,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* We need to coordinate the hotplugs with the asynchronous fbdev
* configuration, for which we use the fbdev->async_cookie.
*/
- if (INTEL_INFO(dev_priv)->num_pipes)
+ if (DEVICE_INFO(dev_priv)->num_pipes)
drm_kms_helper_poll_init(dev);
}
@@ -1305,8 +1305,8 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
if (drm_debug & DRM_UT_DRIVER) {
struct drm_printer p = drm_debug_printer("i915 device info:");
- intel_device_info_dump(&dev_priv->info, &p);
- intel_device_info_dump_runtime(&dev_priv->info, &p);
+ intel_device_info_dump(&dev_priv->device_static, &p);
+ intel_device_info_dump_runtime(&dev_priv->device_static, &p);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@ -1328,8 +1328,8 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
*/
int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
{
- const struct intel_device_info *match_info =
- (struct intel_device_info *)ent->driver_data;
+ const struct intel_device_static_info *match_info =
+ (const struct intel_device_static_info *)ent->driver_data;
struct drm_i915_private *dev_priv;
int ret;
@@ -1383,9 +1383,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
* of the i915_driver_init_/i915_driver_register functions according
* to the role/effect of the given init step.
*/
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (DEVICE_INFO(dev_priv)->num_pipes) {
ret = drm_vblank_init(&dev_priv->drm,
- INTEL_INFO(dev_priv)->num_pipes);
+ DEVICE_INFO(dev_priv)->num_pipes);
if (ret)
goto out_cleanup_hw;
}
@@ -471,7 +471,7 @@ struct i915_gpu_state {
int iommu;
u32 reset_count;
u32 suspend_count;
- struct intel_device_info device_info;
+ struct intel_device_static_info device_static;
struct intel_driver_caps driver_caps;
struct i915_params params;
@@ -1815,7 +1815,7 @@ struct drm_i915_private {
struct kmem_cache *dependencies;
struct kmem_cache *priorities;
- const struct intel_device_info info;
+ const struct intel_device_static_info device_static;
struct intel_driver_caps caps;
/**
@@ -2400,7 +2400,7 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
- for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
+ for (tmp__ = mask__ & DEVICE_INFO(dev_priv__)->ring_mask; \
tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
enum hdmi_force_audio {
@@ -2534,16 +2534,16 @@ static inline unsigned int i915_sg_segment_size(void)
return size;
}
-static inline const struct intel_device_info *
-intel_info(const struct drm_i915_private *dev_priv)
+static inline const struct intel_device_static_info *
+device_info(const struct drm_i915_private *dev_priv)
{
- return &dev_priv->info;
+ return &dev_priv->device_static;
}
-#define INTEL_INFO(dev_priv) intel_info((dev_priv))
+#define DEVICE_INFO(dev_priv) device_info((dev_priv))
-#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
-#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_GEN(dev_priv) (DEVICE_INFO(dev_priv)->gen)
+#define INTEL_DEVID(dev_priv) (DEVICE_INFO(dev_priv)->device_id)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
@@ -2563,7 +2563,7 @@ intel_info(const struct drm_i915_private *dev_priv)
* Use GEN_FOREVER for unbound start and or end.
*/
#define IS_GEN(dev_priv, s, e) \
- (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
+ (!!(DEVICE_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
/*
* Return true if revision is in range [since,until] inclusive.
@@ -2573,7 +2573,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+#define IS_PLATFORM(dev_priv, p) (DEVICE_INFO(dev_priv)->platform_mask & BIT(p))
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
@@ -2595,7 +2595,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
- (dev_priv)->info.gt == 1)
+ DEVICE_INFO(dev_priv)->gt == 1)
#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
@@ -2607,7 +2607,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
+#define IS_MOBILE(dev_priv) (DEVICE_INFO(dev_priv)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
@@ -2618,11 +2618,11 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ DEVICE_INFO(dev_priv)->gt == 3)
#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ DEVICE_INFO(dev_priv)->gt == 3)
/* ULX machines are also considered ULT. */
#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2643,21 +2643,21 @@ intel_info(const struct drm_i915_private *dev_priv)
INTEL_DEVID(dev_priv) == 0x5915 || \
INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ DEVICE_INFO(dev_priv)->gt == 2)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ DEVICE_INFO(dev_priv)->gt == 3)
#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 4)
+ DEVICE_INFO(dev_priv)->gt == 4)
#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ DEVICE_INFO(dev_priv)->gt == 2)
#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ DEVICE_INFO(dev_priv)->gt == 3)
#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (dev_priv)->info.gt == 2)
+ DEVICE_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (dev_priv)->info.gt == 3)
+ DEVICE_INFO(dev_priv)->gt == 3)
#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
@@ -2711,18 +2711,18 @@ intel_info(const struct drm_i915_private *dev_priv)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
-
-#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
+#define IS_GEN2(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv) (!!(DEVICE_INFO(dev_priv)->gen_mask & BIT(10)))
+
+#define IS_LP(dev_priv) (DEVICE_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
@@ -2735,7 +2735,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \
- (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
+ (!!(DEVICE_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
@@ -2744,18 +2744,18 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
-#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
-#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
+#define HAS_LLC(dev_priv) (DEVICE_INFO(dev_priv)->has_llc)
+#define HAS_SNOOP(dev_priv) (DEVICE_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
-#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
+#define HWS_NEEDS_PHYSICAL(dev_priv) (DEVICE_INFO(dev_priv)->hws_needs_physical)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
- ((dev_priv)->info.has_logical_ring_contexts)
+ (DEVICE_INFO(dev_priv)->has_logical_ring_contexts)
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
- ((dev_priv)->info.has_logical_ring_preemption)
+ (DEVICE_INFO(dev_priv)->has_logical_ring_preemption)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
@@ -2764,12 +2764,12 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
- ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
+ ((sizes) & ~DEVICE_INFO(dev_priv)->page_sizes) == 0; \
})
-#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
+#define HAS_OVERLAY(dev_priv) (DEVICE_INFO(dev_priv)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
- ((dev_priv)->info.overlay_needs_physical)
+ (DEVICE_INFO(dev_priv)->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
@@ -2796,39 +2796,39 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
!(IS_I915G(dev_priv) || \
IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
+#define SUPPORTS_TV(dev_priv) (DEVICE_INFO(dev_priv)->supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv) (DEVICE_INFO(dev_priv)->has_hotplug)
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
-#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
+#define HAS_FBC(dev_priv) (DEVICE_INFO(dev_priv)->has_fbc)
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && DEVICE_INFO(dev_priv)->gen >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
-#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
+#define HAS_DP_MST(dev_priv) (DEVICE_INFO(dev_priv)->has_dp_mst)
-#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
-#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
+#define HAS_DDI(dev_priv) (DEVICE_INFO(dev_priv)->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (DEVICE_INFO(dev_priv)->has_fpga_dbg)
+#define HAS_PSR(dev_priv) (DEVICE_INFO(dev_priv)->has_psr)
-#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
-#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
+#define HAS_RC6(dev_priv) (DEVICE_INFO(dev_priv)->has_rc6)
+#define HAS_RC6p(dev_priv) (DEVICE_INFO(dev_priv)->has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
-#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
+#define HAS_CSR(dev_priv) (DEVICE_INFO(dev_priv)->has_csr)
-#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
-#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
+#define HAS_RUNTIME_PM(dev_priv) (DEVICE_INFO(dev_priv)->has_runtime_pm)
+#define HAS_64BIT_RELOC(dev_priv) (DEVICE_INFO(dev_priv)->has_64bit_reloc)
-#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
+#define HAS_IPC(dev_priv) (DEVICE_INFO(dev_priv)->has_ipc)
/*
* For now, anything with a GuC requires uCode loading, and then supports
* command submission once loaded. But these are logically independent
* properties, so we have separate macros to test them.
*/
-#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
-#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
+#define HAS_GUC(dev_priv) (DEVICE_INFO(dev_priv)->has_guc)
+#define HAS_GUC_CT(dev_priv) (DEVICE_INFO(dev_priv)->has_guc_ct)
#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
@@ -2841,9 +2841,9 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
#define USES_HUC(dev_priv) intel_uc_is_using_huc()
-#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
+#define HAS_RESOURCE_STREAMER(dev_priv) (DEVICE_INFO(dev_priv)->has_resource_streamer)
-#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv) (DEVICE_INFO(dev_priv)->has_pooled_eu)
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
@@ -2882,12 +2882,12 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
-#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) (DEVICE_INFO(dev_priv)->has_gmch_display)
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
/* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) (DEVICE_INFO(dev_priv)->has_l3_dpf)
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2 : HAS_L3_DPF(dev_priv))
@@ -3699,10 +3699,10 @@ static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */
/* intel_device_info.c */
-static inline struct intel_device_info *
+static inline struct intel_device_static_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
- return (struct intel_device_info *)&dev_priv->info;
+ return (struct intel_device_static_info *)&dev_priv->device_static;
}
/* modesetting */
@@ -2545,7 +2545,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
unsigned int sg_page_sizes)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = DEVICE_INFO(i915)->page_sizes;
int i;
lockdep_assert_held(&obj->mm.lock);
@@ -5424,10 +5424,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
{
int i;
- if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+ if (DEVICE_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
!IS_CHERRYVIEW(dev_priv))
dev_priv->num_fence_regs = 32;
- else if (INTEL_INFO(dev_priv)->gen >= 4 ||
+ else if (INTEL_GEN(dev_priv) >= 4 ||
IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
dev_priv->num_fence_regs = 16;
@@ -852,7 +852,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->has_llc = HAS_LLC(i915);
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
- cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
+ cache->needs_unfenced = DEVICE_INFO(i915)->unfenced_needs_alignment;
cache->node.allocated = false;
cache->rq = NULL;
cache->rq_size = 0;
@@ -64,7 +64,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
int fence_pitch_shift;
u64 val;
- if (INTEL_INFO(fence->i915)->gen >= 6) {
+ if (INTEL_GEN(fence->i915) >= 6) {
fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
@@ -138,11 +138,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
bool has_full_ppgtt;
bool has_full_48bit_ppgtt;
- if (!dev_priv->info.has_aliasing_ppgtt)
+ if (!DEVICE_INFO(dev_priv)->has_aliasing_ppgtt)
return 0;
- has_full_ppgtt = dev_priv->info.has_full_ppgtt;
- has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+ has_full_ppgtt = DEVICE_INFO(dev_priv)->has_full_ppgtt;
+ has_full_48bit_ppgtt = DEVICE_INFO(dev_priv)->has_full_48bit_ppgtt;
if (intel_vgpu_active(dev_priv)) {
/* GVT-g has no support for 32bit ppgtt */
@@ -826,7 +826,7 @@ static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,
*/
static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
+ ppgtt->pd_dirty_rings = DEVICE_INFO(ppgtt->base.i915)->ring_mask;
}
/* Removes entries from a single page table, releasing it if it's empty.
@@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
ppgtt->base.i915 = dev_priv;
ppgtt->base.dma = &dev_priv->drm.pdev->dev;
- if (INTEL_INFO(dev_priv)->gen < 8)
+ if (INTEL_GEN(dev_priv) < 8)
return gen6_ppgtt_init(ppgtt);
else
return gen8_ppgtt_init(ppgtt);
@@ -356,7 +356,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
reserved_base = 0;
reserved_size = 0;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 2:
case 3:
break;
@@ -579,13 +579,12 @@ static void print_error_obj(struct drm_i915_error_state_buf *m,
}
static void err_print_capabilities(struct drm_i915_error_state_buf *m,
- const struct intel_device_info *info,
- const struct intel_driver_caps *caps)
+ const struct i915_gpu_state *error)
{
struct drm_printer p = i915_error_printer(m);
- intel_device_info_dump_flags(info, &p);
- intel_driver_caps_print(caps, &p);
+ intel_device_info_dump_flags(&error->device_static, &p);
+ intel_driver_caps_print(&error->driver_caps, &p);
}
static void err_print_params(struct drm_i915_error_state_buf *m,
@@ -615,7 +614,7 @@ static void err_print_uc(struct drm_i915_error_state_buf *m,
const struct i915_gpu_state *error =
container_of(error_uc, typeof(*error), uc);
- if (!error->device_info.has_guc)
+ if (!error->device_static.has_guc)
return;
intel_uc_fw_dump(&error_uc->guc_fw, &p);
@@ -662,7 +661,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
err_printf(m, "Reset count: %u\n", error->reset_count);
err_printf(m, "Suspend count: %u\n", error->suspend_count);
- err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
+ err_printf(m, "Platform: %s\n", intel_platform_name(error->device_static.platform));
err_print_pciid(m, error->i915);
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
@@ -810,7 +809,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (error->display)
intel_display_print_error_state(m, error->display);
- err_print_capabilities(m, &error->device_info, &error->driver_caps);
+ err_print_capabilities(m, error);
err_print_params(m, &error->params);
err_print_uc(m, &error->uc);
@@ -1610,7 +1609,7 @@ static void capture_uc_state(struct i915_gpu_state *error)
struct i915_error_uc *error_uc = &error->uc;
/* Capturing uC state won't be useful if there is no GuC */
- if (!error->device_info.has_guc)
+ if (!error->device_static.has_guc)
return;
error_uc->guc_fw = i915->guc.fw;
@@ -1739,9 +1738,7 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
error->reset_count = i915_reset_count(&dev_priv->gpu_error);
error->suspend_count = dev_priv->suspend_count;
- memcpy(&error->device_info,
- INTEL_INFO(dev_priv),
- sizeof(error->device_info));
+ error->device_static = *DEVICE_INFO(dev_priv);
error->driver_caps = dev_priv->caps;
}
@@ -74,19 +74,19 @@
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
-static const struct intel_device_info intel_i830_info = {
+static const struct intel_device_static_info intel_i830_info = {
GEN2_FEATURES,
.platform = INTEL_I830,
.is_mobile = 1, .cursor_needs_physical = 1,
.num_pipes = 2, /* legal, last one wins */
};
-static const struct intel_device_info intel_i845g_info = {
+static const struct intel_device_static_info intel_i845g_info = {
GEN2_FEATURES,
.platform = INTEL_I845G,
};
-static const struct intel_device_info intel_i85x_info = {
+static const struct intel_device_static_info intel_i85x_info = {
GEN2_FEATURES,
.platform = INTEL_I85X, .is_mobile = 1,
.num_pipes = 2, /* legal, last one wins */
@@ -94,7 +94,7 @@ static const struct intel_device_info intel_i85x_info = {
.has_fbc = 1,
};
-static const struct intel_device_info intel_i865g_info = {
+static const struct intel_device_static_info intel_i865g_info = {
GEN2_FEATURES,
.platform = INTEL_I865G,
};
@@ -108,7 +108,7 @@ static const struct intel_device_info intel_i865g_info = {
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
-static const struct intel_device_info intel_i915g_info = {
+static const struct intel_device_static_info intel_i915g_info = {
GEN3_FEATURES,
.platform = INTEL_I915G, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -116,7 +116,7 @@ static const struct intel_device_info intel_i915g_info = {
.unfenced_needs_alignment = 1,
};
-static const struct intel_device_info intel_i915gm_info = {
+static const struct intel_device_static_info intel_i915gm_info = {
GEN3_FEATURES,
.platform = INTEL_I915GM,
.is_mobile = 1,
@@ -128,7 +128,7 @@ static const struct intel_device_info intel_i915gm_info = {
.unfenced_needs_alignment = 1,
};
-static const struct intel_device_info intel_i945g_info = {
+static const struct intel_device_static_info intel_i945g_info = {
GEN3_FEATURES,
.platform = INTEL_I945G,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -137,7 +137,7 @@ static const struct intel_device_info intel_i945g_info = {
.unfenced_needs_alignment = 1,
};
-static const struct intel_device_info intel_i945gm_info = {
+static const struct intel_device_static_info intel_i945gm_info = {
GEN3_FEATURES,
.platform = INTEL_I945GM, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -148,14 +148,14 @@ static const struct intel_device_info intel_i945gm_info = {
.unfenced_needs_alignment = 1,
};
-static const struct intel_device_info intel_g33_info = {
+static const struct intel_device_static_info intel_g33_info = {
GEN3_FEATURES,
.platform = INTEL_G33,
.has_hotplug = 1,
.has_overlay = 1,
};
-static const struct intel_device_info intel_pineview_info = {
+static const struct intel_device_static_info intel_pineview_info = {
GEN3_FEATURES,
.platform = INTEL_PINEVIEW, .is_mobile = 1,
.has_hotplug = 1,
@@ -172,7 +172,7 @@ static const struct intel_device_info intel_pineview_info = {
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
-static const struct intel_device_info intel_i965g_info = {
+static const struct intel_device_static_info intel_i965g_info = {
GEN4_FEATURES,
.platform = INTEL_I965G,
.has_overlay = 1,
@@ -180,7 +180,7 @@ static const struct intel_device_info intel_i965g_info = {
.has_snoop = false,
};
-static const struct intel_device_info intel_i965gm_info = {
+static const struct intel_device_static_info intel_i965gm_info = {
GEN4_FEATURES,
.platform = INTEL_I965GM,
.is_mobile = 1, .has_fbc = 1,
@@ -190,13 +190,13 @@ static const struct intel_device_info intel_i965gm_info = {
.has_snoop = false,
};
-static const struct intel_device_info intel_g45_info = {
+static const struct intel_device_static_info intel_g45_info = {
GEN4_FEATURES,
.platform = INTEL_G45,
.ring_mask = RENDER_RING | BSD_RING,
};
-static const struct intel_device_info intel_gm45_info = {
+static const struct intel_device_static_info intel_gm45_info = {
GEN4_FEATURES,
.platform = INTEL_GM45,
.is_mobile = 1, .has_fbc = 1,
@@ -215,12 +215,12 @@ static const struct intel_device_info intel_gm45_info = {
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
-static const struct intel_device_info intel_ironlake_d_info = {
+static const struct intel_device_static_info intel_ironlake_d_info = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
};
-static const struct intel_device_info intel_ironlake_m_info = {
+static const struct intel_device_static_info intel_ironlake_m_info = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
.is_mobile = 1, .has_fbc = 1,
@@ -243,12 +243,12 @@ static const struct intel_device_info intel_ironlake_m_info = {
GEN6_FEATURES, \
.platform = INTEL_SANDYBRIDGE
-static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+static const struct intel_device_static_info intel_sandybridge_d_gt1_info = {
SNB_D_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+static const struct intel_device_static_info intel_sandybridge_d_gt2_info = {
SNB_D_PLATFORM,
.gt = 2,
};
@@ -259,12 +259,12 @@ static const struct intel_device_info intel_sandybridge_d_gt2_info = {
.is_mobile = 1
-static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+static const struct intel_device_static_info intel_sandybridge_m_gt1_info = {
SNB_M_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+static const struct intel_device_static_info intel_sandybridge_m_gt2_info = {
SNB_M_PLATFORM,
.gt = 2,
};
@@ -288,12 +288,12 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
.platform = INTEL_IVYBRIDGE, \
.has_l3_dpf = 1
-static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+static const struct intel_device_static_info intel_ivybridge_d_gt1_info = {
IVB_D_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+static const struct intel_device_static_info intel_ivybridge_d_gt2_info = {
IVB_D_PLATFORM,
.gt = 2,
};
@@ -304,17 +304,17 @@ static const struct intel_device_info intel_ivybridge_d_gt2_info = {
.is_mobile = 1, \
.has_l3_dpf = 1
-static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+static const struct intel_device_static_info intel_ivybridge_m_gt1_info = {
IVB_M_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+static const struct intel_device_static_info intel_ivybridge_m_gt2_info = {
IVB_M_PLATFORM,
.gt = 2,
};
-static const struct intel_device_info intel_ivybridge_q_info = {
+static const struct intel_device_static_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
.gt = 2,
@@ -322,7 +322,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
.has_l3_dpf = 1,
};
-static const struct intel_device_info intel_valleyview_info = {
+static const struct intel_device_static_info intel_valleyview_info = {
.platform = INTEL_VALLEYVIEW,
.gen = 7,
.is_lp = 1,
@@ -358,17 +358,17 @@ static const struct intel_device_info intel_valleyview_info = {
.platform = INTEL_HASWELL, \
.has_l3_dpf = 1
-static const struct intel_device_info intel_haswell_gt1_info = {
+static const struct intel_device_static_info intel_haswell_gt1_info = {
HSW_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_haswell_gt2_info = {
+static const struct intel_device_static_info intel_haswell_gt2_info = {
HSW_PLATFORM,
.gt = 2,
};
-static const struct intel_device_info intel_haswell_gt3_info = {
+static const struct intel_device_static_info intel_haswell_gt3_info = {
HSW_PLATFORM,
.gt = 3,
};
@@ -388,17 +388,17 @@ static const struct intel_device_info intel_haswell_gt3_info = {
.gen = 8, \
.platform = INTEL_BROADWELL
-static const struct intel_device_info intel_broadwell_gt1_info = {
+static const struct intel_device_static_info intel_broadwell_gt1_info = {
BDW_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_broadwell_gt2_info = {
+static const struct intel_device_static_info intel_broadwell_gt2_info = {
BDW_PLATFORM,
.gt = 2,
};
-static const struct intel_device_info intel_broadwell_rsvd_info = {
+static const struct intel_device_static_info intel_broadwell_rsvd_info = {
BDW_PLATFORM,
.gt = 3,
/* According to the device ID those devices are GT3, they were
@@ -406,13 +406,13 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
*/
};
-static const struct intel_device_info intel_broadwell_gt3_info = {
+static const struct intel_device_static_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
-static const struct intel_device_info intel_cherryview_info = {
+static const struct intel_device_static_info intel_cherryview_info = {
.gen = 8, .num_pipes = 3,
.has_hotplug = 1,
.is_lp = 1,
@@ -455,12 +455,12 @@ static const struct intel_device_info intel_cherryview_info = {
.gen = 9, \
.platform = INTEL_SKYLAKE
-static const struct intel_device_info intel_skylake_gt1_info = {
+static const struct intel_device_static_info intel_skylake_gt1_info = {
SKL_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_skylake_gt2_info = {
+static const struct intel_device_static_info intel_skylake_gt2_info = {
SKL_PLATFORM,
.gt = 2,
};
@@ -470,12 +470,12 @@ static const struct intel_device_info intel_skylake_gt2_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
-static const struct intel_device_info intel_skylake_gt3_info = {
+static const struct intel_device_static_info intel_skylake_gt3_info = {
SKL_GT3_PLUS_PLATFORM,
.gt = 3,
};
-static const struct intel_device_info intel_skylake_gt4_info = {
+static const struct intel_device_static_info intel_skylake_gt4_info = {
SKL_GT3_PLUS_PLATFORM,
.gt = 4,
};
@@ -511,13 +511,13 @@ static const struct intel_device_info intel_skylake_gt4_info = {
IVB_CURSOR_OFFSETS, \
BDW_COLORS
-static const struct intel_device_info intel_broxton_info = {
+static const struct intel_device_static_info intel_broxton_info = {
GEN9_LP_FEATURES,
.platform = INTEL_BROXTON,
.ddb_size = 512,
};
-static const struct intel_device_info intel_geminilake_info = {
+static const struct intel_device_static_info intel_geminilake_info = {
GEN9_LP_FEATURES,
.platform = INTEL_GEMINILAKE,
.ddb_size = 1024,
@@ -529,17 +529,17 @@ static const struct intel_device_info intel_geminilake_info = {
.gen = 9, \
.platform = INTEL_KABYLAKE
-static const struct intel_device_info intel_kabylake_gt1_info = {
+static const struct intel_device_static_info intel_kabylake_gt1_info = {
KBL_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_kabylake_gt2_info = {
+static const struct intel_device_static_info intel_kabylake_gt2_info = {
KBL_PLATFORM,
.gt = 2,
};
-static const struct intel_device_info intel_kabylake_gt3_info = {
+static const struct intel_device_static_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@ -550,17 +550,17 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
.gen = 9, \
.platform = INTEL_COFFEELAKE
-static const struct intel_device_info intel_coffeelake_gt1_info = {
+static const struct intel_device_static_info intel_coffeelake_gt1_info = {
CFL_PLATFORM,
.gt = 1,
};
-static const struct intel_device_info intel_coffeelake_gt2_info = {
+static const struct intel_device_static_info intel_coffeelake_gt2_info = {
CFL_PLATFORM,
.gt = 2,
};
-static const struct intel_device_info intel_coffeelake_gt3_info = {
+static const struct intel_device_static_info intel_coffeelake_gt3_info = {
CFL_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@ -571,7 +571,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
.ddb_size = 1024, \
GLK_COLORS
-static const struct intel_device_info intel_cannonlake_info = {
+static const struct intel_device_static_info intel_cannonlake_info = {
GEN10_FEATURES,
.is_alpha_support = 1,
.platform = INTEL_CANNONLAKE,
@@ -585,7 +585,7 @@ static const struct intel_device_info intel_cannonlake_info = {
.ddb_size = 2048, \
.has_csr = 0
-static const struct intel_device_info intel_icelake_11_info = {
+static const struct intel_device_static_info intel_icelake_11_info = {
GEN11_FEATURES,
.platform = INTEL_ICELAKE,
.is_alpha_support = 1,
@@ -664,8 +664,8 @@ static void i915_pci_remove(struct pci_dev *pdev)
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
- struct intel_device_info *intel_info =
- (struct intel_device_info *) ent->driver_data;
+ struct intel_device_static_info *intel_info =
+ (struct intel_device_static_info *) ent->driver_data;
int err;
if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
@@ -2691,7 +2691,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
{
return div64_u64(1000000000ULL * (2ULL << exponent),
- 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
+ 1000ULL * DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz);
}
/**
@@ -3510,7 +3510,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
oa_sample_rate_hard_limit = 1000 *
- (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
+ (DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
mutex_init(&dev_priv->perf.metrics_lock);
@@ -3134,9 +3134,9 @@ enum i915_power_well_id {
/*
* Clock control & power management
*/
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define _DPLL_A (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6014)
+#define _DPLL_B (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6030)
#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
#define VGA0 _MMIO(0x6000)
@@ -3233,9 +3233,9 @@ enum i915_power_well_id {
#define SDVO_MULTIPLIER_SHIFT_HIRES 4
#define SDVO_MULTIPLIER_SHIFT_VGA 0
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define _DPLL_A_MD (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x601c)
+#define _DPLL_B_MD (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x603c)
#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
/*
@@ -3307,7 +3307,7 @@ enum i915_power_well_id {
#define DSTATE_PLL_D3_OFF (1<<3)
#define DSTATE_GFX_CLOCK_GATING (1<<1)
#define DSTATE_DOT_CLOCK_GATING (1<<0)
-#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -3447,8 +3447,8 @@ enum i915_power_well_id {
#define PALETTE_A_OFFSET 0xa000
#define PALETTE_B_OFFSET 0xa800
#define CHV_PALETTE_C_OFFSET 0xc000
-#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
- dev_priv->info.display_mmio_offset + (i) * 4)
+#define PALETTE(pipe, i) _MMIO(DEVICE_INFO(dev_priv)->palette_offsets[pipe] + \
+ DEVICE_INFO(dev_priv)->display_mmio_offset + (i) * 4)
/* MCH MMIO space */
@@ -4020,9 +4020,9 @@ enum {
#define CHV_TRANSCODER_C_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
-#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
- dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg) _MMIO(DEVICE_INFO(dev_priv)->trans_offsets[(pipe)] - \
+ DEVICE_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
+ DEVICE_INFO(dev_priv)->display_mmio_offset)
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
@@ -4204,7 +4204,7 @@ enum {
/* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61110)
#define PORTB_HOTPLUG_INT_EN (1 << 29)
#define PORTC_HOTPLUG_INT_EN (1 << 28)
#define PORTD_HOTPLUG_INT_EN (1 << 27)
@@ -4234,7 +4234,7 @@ enum {
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
-#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61114)
/*
* HDMI/DP bits are g4x+
*
@@ -4316,7 +4316,7 @@ enum {
#define PORT_DFT_I9XX _MMIO(0x61150)
#define DC_BALANCE_RESET (1 << 25)
-#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
+#define PORT_DFT2_G4X _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61154)
#define DC_BALANCE_RESET_VLV (1 << 31)
#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
@@ -4573,7 +4573,7 @@ enum {
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* Panel fitting */
-#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
+#define PFIT_CONTROL _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61230)
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
@@ -4591,7 +4591,7 @@ enum {
#define PFIT_SCALING_PROGRAMMED (1 << 26)
#define PFIT_SCALING_PILLAR (2 << 26)
#define PFIT_SCALING_LETTER (3 << 26)
-#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61234)
/* Pre-965 */
#define PFIT_VERT_SCALE_SHIFT 20
#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -4603,25 +4603,25 @@ enum {
#define PFIT_HORIZ_SCALE_SHIFT_965 0
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
-#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61238)
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61350)
#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
_VLV_BLC_PWM_CTL2_B)
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61354)
#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
_VLV_BLC_PWM_CTL_B)
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61360)
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
_VLV_BLC_HIST_CTL_B)
/* Backlight control */
-#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2 _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
#define BLM_PWM_ENABLE (1 << 31)
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
#define BLM_PIPE_SELECT (1 << 29)
@@ -4644,7 +4644,7 @@ enum {
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
#define BLM_PHASE_IN_INCR_SHIFT (0)
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
-#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61254)
/*
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
@@ -4666,7 +4666,7 @@ enum {
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
-#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x61260)
#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
@@ -5285,40 +5285,40 @@ enum {
* is 20 bytes in each direction, hence the 5 fixed
* data registers
*/
-#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
-#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
-#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
-#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
-#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
-#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
-
-#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
-#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
-#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
-#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
-#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
-#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
-
-#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
-#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
-#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
-#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
-#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
-#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
-
-#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
-#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
-#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
-#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
-#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
-#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
-
-#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
-#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
-#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
-#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
-#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
-#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+#define _DPA_AUX_CH_CTL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64324)
+
+#define _DPF_AUX_CH_CTL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x64524)
#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -5517,9 +5517,9 @@ enum {
*/
#define PIPE_EDP_OFFSET 0x7f000
-#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
- dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
+#define _MMIO_PIPE2(pipe, reg) _MMIO(DEVICE_INFO(dev_priv)->pipe_offsets[pipe] - \
+ DEVICE_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
+ DEVICE_INFO(dev_priv)->display_mmio_offset)
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
@@ -5593,7 +5593,7 @@ enum {
#define DPINVGTT_STATUS_MASK 0xff
#define DPINVGTT_STATUS_MASK_CHV 0xfff
-#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
+#define DSPARB _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x70030)
#define DSPARB_CSTART_MASK (0x7f << 7)
#define DSPARB_CSTART_SHIFT 7
#define DSPARB_BSTART_MASK (0x7f)
@@ -5628,7 +5628,7 @@ enum {
#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
/* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
+#define DSPFW1 _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x70034)
#define DSPFW_SR_SHIFT 23
#define DSPFW_SR_MASK (0x1ff<<23)
#define DSPFW_CURSORB_SHIFT 16
@@ -5639,7 +5639,7 @@ enum {
#define DSPFW_PLANEA_SHIFT 0
#define DSPFW_PLANEA_MASK (0x7f<<0)
#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
-#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
+#define DSPFW2 _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x70038)
#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
#define DSPFW_FBC_SR_SHIFT 28
#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
@@ -5655,7 +5655,7 @@ enum {
#define DSPFW_SPRITEA_SHIFT 0
#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
-#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
+#define DSPFW3 _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x7003c)
#define DSPFW_HPLL_SR_EN (1<<31)
#define PINEVIEW_SELF_REFRESH_EN (1<<30)
#define DSPFW_CURSOR_SR_SHIFT 24
@@ -5965,9 +5965,9 @@ enum {
#define _CURBBASE_IVB 0x71084
#define _CURBPOS_IVB 0x71088
-#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
- dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
+#define _CURSOR2(pipe, reg) _MMIO(DEVICE_INFO(dev_priv)->cursor_offsets[(pipe)] - \
+ DEVICE_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
+ DEVICE_INFO(dev_priv)->display_mmio_offset)
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
@@ -6071,35 +6071,35 @@ enum {
* [10:1f] all
* [30:32] all
*/
-#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
-#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
-#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF0(i) _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i) _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i) _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
/* Pipe B */
-#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
-#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
-#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
+#define _PIPEBDSL (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71000)
+#define _PIPEBCONF (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71008)
+#define _PIPEBSTAT (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71024)
#define _PIPEBFRAMEHIGH 0x71040
#define _PIPEBFRAMEPIXEL 0x71044
-#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71044)
/* Display B control */
-#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
+#define _DSPBCNTR (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71180)
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
-#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
-#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
-#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
-#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
+#define _DSPBADDR (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71188)
+#define _DSPBPOS (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x7118C)
+#define _DSPBSIZE (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x71190)
+#define _DSPBSURF (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE (DEVICE_INFO(dev_priv)->display_mmio_offset + 0x711AC)
/* Sprite A control */
#define _DVSACNTR 0x72180
@@ -8301,7 +8301,7 @@ enum {
#define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
/* Audio */
-#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID _MMIO(DEVICE_INFO(dev_priv)->display_mmio_offset + 0x62020)
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
#define INTEL_AUDIO_DEVCTG 0x80862802
@@ -9693,8 +9693,8 @@ enum skl_power_gate {
#define READ_DATA_VALID(n) (1 << (n))
/* For UMS only (deprecated): */
-#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
-#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
+#define _PALETTE_A (DEVICE_INFO(dev_priv)->display_mmio_offset + 0xa000)
+#define _PALETTE_B (DEVICE_INFO(dev_priv)->display_mmio_offset + 0xa800)
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
@@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
- } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
+ } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -950,7 +950,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
{
int ret;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (DEVICE_INFO(dev_priv)->num_pipes == 0)
return;
ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
@@ -391,7 +391,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
bool alternate)
{
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 2:
return alternate ? 66667 : 48000;
case 3:
@@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
return max_cdclk_freq;
else if (IS_CHERRYVIEW(dev_priv))
return max_cdclk_freq*95/100;
- else if (INTEL_INFO(dev_priv)->gen < 4)
+ else if (INTEL_GEN(dev_priv) < 4)
return 2*max_cdclk_freq*90/100;
else
return max_cdclk_freq*90/100;
@@ -387,7 +387,7 @@ static void bdw_load_degamma_lut(struct drm_crtc_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
- uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ uint32_t i, lut_size = DEVICE_INFO(dev_priv)->color.degamma_lut_size;
I915_WRITE(PREC_PAL_INDEX(pipe),
PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
@@ -418,7 +418,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
{
struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
- uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ uint32_t i, lut_size = DEVICE_INFO(dev_priv)->color.gamma_lut_size;
WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
@@ -476,7 +476,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
bdw_load_degamma_lut(state);
bdw_load_gamma_lut(state,
- INTEL_INFO(dev_priv)->color.degamma_lut_size);
+ DEVICE_INFO(dev_priv)->color.degamma_lut_size);
intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
@@ -562,7 +562,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
if (state->degamma_lut) {
lut = (struct drm_color_lut *) state->degamma_lut->data;
- lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ lut_size = DEVICE_INFO(dev_priv)->color.degamma_lut_size;
for (i = 0; i < lut_size; i++) {
/* Write LUT in U0.14 format. */
word0 =
@@ -577,7 +577,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
if (state->gamma_lut) {
lut = (struct drm_color_lut *) state->gamma_lut->data;
- lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ lut_size = DEVICE_INFO(dev_priv)->color.gamma_lut_size;
for (i = 0; i < lut_size; i++) {
/* Write LUT in U0.10 format. */
word0 =
@@ -616,9 +616,9 @@ int intel_color_check(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
size_t gamma_length, degamma_length;
- degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
+ degamma_length = DEVICE_INFO(dev_priv)->color.degamma_lut_size *
sizeof(struct drm_color_lut);
- gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
+ gamma_length = DEVICE_INFO(dev_priv)->color.gamma_lut_size *
sizeof(struct drm_color_lut);
/*
@@ -665,10 +665,10 @@ void intel_color_init(struct drm_crtc *crtc)
}
/* Enable color management support when we have degamma & gamma LUTs. */
- if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
- INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
+ if (DEVICE_INFO(dev_priv)->color.degamma_lut_size != 0 &&
+ DEVICE_INFO(dev_priv)->color.gamma_lut_size != 0)
drm_crtc_enable_color_mgmt(crtc,
- INTEL_INFO(dev_priv)->color.degamma_lut_size,
+ DEVICE_INFO(dev_priv)->color.degamma_lut_size,
true,
- INTEL_INFO(dev_priv)->color.gamma_lut_size);
+ DEVICE_INFO(dev_priv)->color.gamma_lut_size);
}
@@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
I915_WRITE(DPLL_CTRL2, val);
- } else if (INTEL_INFO(dev_priv)->gen < 9) {
+ } else if (INTEL_GEN(dev_priv) < 9) {
I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
}
@@ -71,7 +71,7 @@ const char *intel_platform_name(enum intel_platform platform)
return platform_names[platform];
}
-void intel_device_info_dump_flags(const struct intel_device_info *info,
+void intel_device_info_dump_flags(const struct intel_device_static_info *info,
struct drm_printer *p)
{
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
@@ -96,7 +96,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
}
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
+void intel_device_info_dump_runtime(const struct intel_device_static_info *info,
struct drm_printer *p)
{
sseu_dump(&info->sseu, p);
@@ -105,11 +105,11 @@ void intel_device_info_dump_runtime(const struct intel_device_info *info,
info->cs_timestamp_frequency_khz);
}
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(const struct intel_device_static_info *info,
struct drm_printer *p)
{
struct drm_i915_private *dev_priv =
- container_of(info, struct drm_i915_private, info);
+ container_of(info, struct drm_i915_private, device_static);
drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
INTEL_DEVID(dev_priv),
@@ -195,7 +195,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct intel_device_static_info *info = mkwrite_device_info(dev_priv);
struct sseu_dev_info *sseu = &info->sseu;
int s_max = 3, ss_max = 4, eu_max = 8;
int s, ss;
@@ -462,7 +462,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* intel_device_info_runtime_init - initialize runtime info
* @info: intel device info struct
*
- * Determine various intel_device_info fields at runtime.
+ * Determine various intel_device_static_info fields at runtime.
*
* Use it when either:
* - it's judged too laborious to fill n static structures with the limit
@@ -474,10 +474,10 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* - after the PCH has been detected,
* - before the first usage of the fields it can tweak.
*/
-void intel_device_info_runtime_init(struct intel_device_info *info)
+void intel_device_info_runtime_init(struct intel_device_static_info *info)
{
struct drm_i915_private *dev_priv =
- container_of(info, struct drm_i915_private, info);
+ container_of(info, struct drm_i915_private, device_static);
enum pipe pipe;
if (INTEL_GEN(dev_priv) >= 10) {
@@ -125,7 +125,7 @@ struct sseu_dev_info {
u8 has_eu_pg:1;
};
-struct intel_device_info {
+struct intel_device_static_info {
u16 device_id;
u16 gen_mask;
@@ -178,12 +178,12 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
const char *intel_platform_name(enum intel_platform platform);
-void intel_device_info_runtime_init(struct intel_device_info *info);
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_runtime_init(struct intel_device_static_info *info);
+void intel_device_info_dump(const struct intel_device_static_info *info,
struct drm_printer *p);
-void intel_device_info_dump_flags(const struct intel_device_info *info,
+void intel_device_info_dump_flags(const struct intel_device_static_info *info,
struct drm_printer *p);
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
+void intel_device_info_dump_runtime(const struct intel_device_static_info *info,
struct drm_printer *p);
void intel_driver_caps_print(const struct intel_driver_caps *caps,
@@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev_priv)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return 128 * 1024;
- else if (INTEL_INFO(dev_priv)->gen >= 4)
+ else if (INTEL_GEN(dev_priv) >= 4)
return 4 * 1024;
else
return 0;
@@ -6156,7 +6156,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
}
- if (INTEL_INFO(dev_priv)->num_pipes == 2)
+ if (DEVICE_INFO(dev_priv)->num_pipes == 2)
return 0;
/* Ivybridge 3 pipe is really complicated */
@@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* GDG double wide on either pipe, otherwise pipe A only */
- return INTEL_INFO(dev_priv)->gen < 4 &&
+ return DEVICE_INFO(dev_priv)->gen < 4 &&
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}
@@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *config = intel_crtc->config;
- if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
+ if (IS_BROADWELL(dev_priv) || DEVICE_INFO(dev_priv)->gen >= 9) {
u32 val = 0;
switch (intel_crtc->config->pipe_bpp) {
@@ -8309,7 +8309,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
* clear if it''s a win or loss power wise. No point in doing
* this on ILK at all since it has a fixed DPLL<->pipe mapping.
*/
- if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+ if (DEVICE_INFO(dev_priv)->num_pipes == 3 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
dpll |= DPLL_SDVO_HIGH_SPEED;
@@ -9300,7 +9300,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
u32 base;
- if (INTEL_INFO(dev_priv)->cursor_needs_physical)
+ if (DEVICE_INFO(dev_priv)->cursor_needs_physical)
base = obj->phys_handle->busaddr;
else
base = intel_plane_ggtt_offset(plane_state);
@@ -12688,7 +12688,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
if (plane->type == DRM_PLANE_TYPE_CURSOR &&
- INTEL_INFO(dev_priv)->cursor_needs_physical) {
+ DEVICE_INFO(dev_priv)->cursor_needs_physical) {
const int align = intel_cursor_alignment(dev_priv);
ret = i915_gem_object_attach_phys(obj, align);
@@ -13102,7 +13102,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
if (ret)
goto out_free;
- if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
+ if (DEVICE_INFO(dev_priv)->cursor_needs_physical) {
int align = intel_cursor_alignment(dev_priv);
ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
@@ -13390,7 +13390,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int i;
- crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
+ crtc->num_scalers = DEVICE_INFO(dev_priv)->num_scalers[crtc->pipe];
if (!crtc->num_scalers)
return;
@@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
* gen2/3 display engine uses the fence if present,
* so the tiling mode must match the fb modifier exactly.
*/
- if (INTEL_INFO(dev_priv)->gen < 4 &&
+ if (DEVICE_INFO(dev_priv)->gen < 4 &&
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
goto err;
@@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
{
intel_init_cdclk_hooks(dev_priv);
- if (INTEL_INFO(dev_priv)->gen >= 9) {
+ if (DEVICE_INFO(dev_priv)->gen >= 9) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
skylake_get_initial_plane_config;
@@ -14556,7 +14556,7 @@ int intel_modeset_init(struct drm_device *dev)
intel_init_pm(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (DEVICE_INFO(dev_priv)->num_pipes == 0)
return 0;
/*
@@ -14602,8 +14602,8 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.fb_base = ggtt->gmadr.start;
DRM_DEBUG_KMS("%d display pipe%s available.\n",
- INTEL_INFO(dev_priv)->num_pipes,
- INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
+ DEVICE_INFO(dev_priv)->num_pipes,
+ DEVICE_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
for_each_pipe(dev_priv, pipe) {
int ret;
@@ -15443,7 +15443,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
};
int i;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (DEVICE_INFO(dev_priv)->num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
@@ -15485,7 +15485,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
+ error->num_transcoders = DEVICE_INFO(dev_priv)->num_pipes;
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
@@ -15524,7 +15524,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
if (!error)
return;
- err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
+ err_printf(m, "Num Pipes: %d\n", DEVICE_INFO(dev_priv)->num_pipes);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
@@ -85,7 +85,7 @@ enum i9xx_plane_id {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * DEVICE_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
/*
* Per-pipe plane identifier.
@@ -200,20 +200,20 @@ struct intel_link_m_n {
};
#define for_each_pipe(__dev_priv, __p) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
+ for ((__p) = 0; (__p) < DEVICE_INFO(__dev_priv)->num_pipes; (__p)++)
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
+ for ((__p) = 0; (__p) < DEVICE_INFO(__dev_priv)->num_pipes; (__p)++) \
for_each_if((__mask) & BIT(__p))
#define for_each_universal_plane(__dev_priv, __pipe, __p) \
for ((__p) = 0; \
- (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
+ (__p) < DEVICE_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
(__p)++)
#define for_each_sprite(__dev_priv, __p, __s) \
for ((__s) = 0; \
- (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
+ (__s) < DEVICE_INFO(__dev_priv)->num_sprites[(__p)]; \
(__s)++)
#define for_each_port_masked(__port, __ports_mask) \
@@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
enum port port)
{
- if (INTEL_INFO(dev_priv)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return skl_aux_ctl_reg(dev_priv, port);
else if (HAS_PCH_SPLIT(dev_priv))
return ilk_aux_ctl_reg(dev_priv, port);
@@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
enum port port, int index)
{
- if (INTEL_INFO(dev_priv)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return skl_aux_data_reg(dev_priv, port, index);
else if (HAS_PCH_SPLIT(dev_priv))
return ilk_aux_data_reg(dev_priv, port, index);
@@ -263,8 +263,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
*/
int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
- const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
+ struct intel_device_static_info *info = mkwrite_device_info(dev_priv);
+ const unsigned int ring_mask = DEVICE_INFO(dev_priv)->ring_mask;
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned int mask = 0;
@@ -292,7 +292,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
* engines.
*/
if (WARN_ON(mask != ring_mask))
- device_info->ring_mask = mask;
+ info->ring_mask = mask;
/* We always presume we have at least RCS available for later probing */
if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
@@ -300,7 +300,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
goto cleanup;
}
- device_info->num_rings = hweight32(mask);
+ info->num_rings = hweight32(mask);
i915_check_and_clear_faults(dev_priv);
@@ -1136,7 +1136,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
+ if (!is_power_of_2(DEVICE_INFO(dev_priv)->sseu.subslice_7eu[i]))
continue;
/*
@@ -1145,7 +1145,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
+ ss = ffs(DEVICE_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
@@ -476,7 +476,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
* fbdev helper library.
*/
if (num_connectors_enabled != num_connectors_detected &&
- num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
+ num_connectors_enabled < DEVICE_INFO(dev_priv)->num_pipes) {
DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
num_connectors_detected);
@@ -664,7 +664,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+ if (WARN_ON(DEVICE_INFO(dev_priv)->num_pipes == 0))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
@@ -975,7 +975,7 @@ static int guc_clients_create(struct intel_guc *guc)
GEM_BUG_ON(guc->preempt_client);
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ DEVICE_INFO(dev_priv)->ring_mask,
GUC_CLIENT_PRIORITY_KMD_NORMAL,
dev_priv->kernel_context);
if (IS_ERR(client)) {
@@ -986,7 +986,7 @@ static int guc_clients_create(struct intel_guc *guc)
if (dev_priv->preempt_context) {
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ DEVICE_INFO(dev_priv)->ring_mask,
GUC_CLIENT_PRIORITY_KMD_HIGH,
dev_priv->preempt_context);
if (IS_ERR(client)) {
@@ -110,7 +110,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
pinfo.size_data = sizeof(*pdata);
pinfo.dma_mask = DMA_BIT_MASK(32);
- pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
+ pdata->num_pipes = DEVICE_INFO(dev_priv)->num_pipes;
pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
pdata->port[0].pipe = -1;
pdata->port[1].pipe = -1;
@@ -2120,24 +2120,24 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (DEVICE_INFO(dev_priv)->sseu.has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
+ rpcs |= hweight8(DEVICE_INFO(dev_priv)->sseu.slice_mask) <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
+ if (DEVICE_INFO(dev_priv)->sseu.has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
+ rpcs |= hweight8(DEVICE_INFO(dev_priv)->sseu.subslice_mask) <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
- rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+ if (DEVICE_INFO(dev_priv)->sseu.has_eu_pg) {
+ rpcs |= DEVICE_INFO(dev_priv)->sseu.eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+ rpcs |= DEVICE_INFO(dev_priv)->sseu.eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
@@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
/* Convert from 100ms to 100us units */
pps->t4 = val * 1000;
- if (INTEL_INFO(dev_priv)->gen <= 4 &&
+ if (INTEL_GEN(dev_priv) <= 4 &&
pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
DRM_DEBUG_KMS("Panel power timings uninitialized, "
"setting defaults\n");
@@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
table->table = broxton_mocs_table;
result = true;
} else {
- WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
+ WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
"Platform that should have a MOCS table does not.\n");
}
@@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
u32 val;
val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
- if (INTEL_INFO(dev_priv)->gen < 4)
+ if (INTEL_GEN(dev_priv) < 4)
val >>= 1;
if (panel->backlight.combination_mode) {
@@ -42,7 +42,7 @@ static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
struct drm_i915_private *dev_priv = info->dev_priv;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
- if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
+ if (info->pipe >= DEVICE_INFO(dev_priv)->num_pipes)
return -ENODEV;
spin_lock_irq(&pipe_crc->lock);
@@ -778,7 +778,7 @@ static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
{
const char name = buf[0];
- if (name < 'A' || name >= pipe_name(INTEL_INFO(dev_priv)->num_pipes))
+ if (name < 'A' || name >= pipe_name(DEVICE_INFO(dev_priv)->num_pipes))
return -EINVAL;
*pipe = name - 'A';
@@ -1897,7 +1897,8 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for (level = 0; level < wm_state->num_levels; level++) {
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
- const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
+ const int sr_fifo_size =
+ DEVICE_INFO(dev_priv)->num_pipes * 512 - 1;
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
break;
@@ -2630,7 +2631,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
+ fifo_size /= DEVICE_INFO(dev_priv)->num_pipes;
/*
* For some reason the non self refresh
@@ -3782,7 +3783,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+ ddb_size = DEVICE_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
if (INTEL_GEN(dev_priv) < 11)
@@ -6526,7 +6527,7 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
static bool sanitize_rc6(struct drm_i915_private *i915)
{
- struct intel_device_info *info = mkwrite_device_info(i915);
+ struct intel_device_static_info *info = mkwrite_device_info(i915);
/* Powersaving is controlled by the host when inside a VM */
if (intel_vgpu_active(i915))
@@ -6943,7 +6944,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
* No floor required for ring frequency on SKL.
*/
ring_freq = gpu_freq;
- } else if (INTEL_INFO(dev_priv)->gen >= 8) {
+ } else if (DEVICE_INFO(dev_priv)->gen >= 8) {
/* max(2 * GT, DDR). NB: GT is 50MHz units */
ring_freq = max(min_ring_freq, gpu_freq);
} else if (IS_HASWELL(dev_priv)) {
@@ -6979,7 +6980,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
+ switch (DEVICE_INFO(dev_priv)->sseu.eu_total) {
case 8:
/* (2 * 4) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
@@ -7554,7 +7555,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
unsigned long val;
- if (INTEL_INFO(dev_priv)->gen != 5)
+ if (DEVICE_INFO(dev_priv)->gen != 5)
return 0;
spin_lock_irq(&mchdev_lock);
@@ -7597,7 +7598,7 @@ static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
const int vd = _pxvid_to_vd(pxvid);
const int vm = vd - 1125;
- if (INTEL_INFO(dev_priv)->is_mobile)
+ if (DEVICE_INFO(dev_priv)->is_mobile)
return vm > 0 ? vm : 0;
return vd;
@@ -7638,7 +7639,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev_priv)->gen != 5)
+ if (DEVICE_INFO(dev_priv)->gen != 5)
return;
spin_lock_irq(&mchdev_lock);
@@ -7689,7 +7690,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{
unsigned long val;
- if (INTEL_INFO(dev_priv)->gen != 5)
+ if (DEVICE_INFO(dev_priv)->gen != 5)
return 0;
spin_lock_irq(&mchdev_lock);
@@ -9116,7 +9117,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev_priv)) {
- if (INTEL_INFO(dev_priv)->num_pipes == 1) {
+ if (DEVICE_INFO(dev_priv)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
} else {
@@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
enum port port)
{
- if (INTEL_INFO(dev_priv)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return DP_AUX_CH_CTL(port);
else
return EDP_PSR_AUX_CTL;
@@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
enum port port, int index)
{
- if (INTEL_INFO(dev_priv)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return DP_AUX_CH_DATA(port, index);
else
return EDP_PSR_AUX_DATA(index);
@@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (IS_GEN(dev_priv, 6, 7))
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (INTEL_INFO(dev_priv)->gen >= 6)
+ if (INTEL_GEN(dev_priv) >= 6)
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
return init_workarounds_ring(engine);
@@ -1385,7 +1385,7 @@ static inline int mi_set_context(struct drm_i915_gem_request *rq, u32 flags)
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
- INTEL_INFO(i915)->num_rings - 1 :
+ DEVICE_INFO(i915)->num_rings - 1 :
0;
int len;
u32 *cs;
@@ -2005,7 +2005,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
- num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
+ num_rings = DEVICE_INFO(dev_priv)->num_rings - 1;
engine->emit_breadcrumb_sz += num_rings * 3;
if (num_rings & 1)
engine->emit_breadcrumb_sz++;
@@ -86,11 +86,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
#define instdone_slice_mask(dev_priv__) \
(INTEL_GEN(dev_priv__) == 7 ? \
- 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
+ 1 : DEVICE_INFO(dev_priv__)->sseu.slice_mask)
#define instdone_subslice_mask(dev_priv__) \
(INTEL_GEN(dev_priv__) == 7 ? \
- 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
+ 1 : DEVICE_INFO(dev_priv__)->sseu.subslice_mask)
#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
for ((slice__) = 0, (subslice__) = 0; \
@@ -1475,7 +1475,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
GEM_BUG_ON(entry->size > 8);
GEM_BUG_ON(entry_offset & (entry->size - 1));
- if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
+ if (DEVICE_INFO(dev_priv)->gen_mask & entry->gen_mask &&
entry_offset == (reg->offset & -entry->size))
break;
entry++;
@@ -1883,9 +1883,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
if (!i915_modparams.reset)
return NULL;
- if (INTEL_INFO(dev_priv)->gen >= 8)
+ if (DEVICE_INFO(dev_priv)->gen >= 8)
return gen8_reset_engines;
- else if (INTEL_INFO(dev_priv)->gen >= 6)
+ else if (DEVICE_INFO(dev_priv)->gen >= 6)
return gen6_reset_engines;
else if (IS_GEN5(dev_priv))
return ironlake_do_reset;
@@ -1893,7 +1893,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
return g4x_do_reset;
else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
return g33_do_reset;
- else if (INTEL_INFO(dev_priv)->gen >= 3)
+ else if (DEVICE_INFO(dev_priv)->gen >= 3)
return i915_do_reset;
else
return NULL;
@@ -1946,7 +1946,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
{
- return (dev_priv->info.has_reset_engine &&
+ return (DEVICE_INFO(dev_priv)->has_reset_engine &&
i915_modparams.reset >= 2);
}
@@ -339,7 +339,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
static int igt_check_page_sizes(struct i915_vma *vma)
{
struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
- unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ unsigned int supported = DEVICE_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj = vma->obj;
int err = 0;
@@ -380,7 +380,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->base.i915;
- unsigned int saved_mask = INTEL_INFO(i915)->page_sizes;
+ unsigned int saved_mask = DEVICE_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
int i, j, single;
@@ -459,7 +459,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->base.i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = DEVICE_INFO(i915)->page_sizes;
struct drm_i915_gem_object *obj;
int bit;
int err;
@@ -1181,7 +1181,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = DEVICE_INFO(i915)->page_sizes;
static unsigned int pages[ARRAY_SIZE(page_sizes)];
struct drm_i915_gem_object *obj;
unsigned int size_mask;
@@ -1408,7 +1408,7 @@ static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *dev_priv = ctx->i915;
- unsigned long supported = INTEL_INFO(dev_priv)->page_sizes;
+ unsigned long supported = DEVICE_INFO(dev_priv)->page_sizes;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -396,7 +396,7 @@ static int igt_ctx_exec(void *arg)
ncontexts++;
}
pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
- ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
+ ncontexts, DEVICE_INFO(i915)->num_rings, ndwords);
dw = 0;
list_for_each_entry(obj, &objects, st_link) {
@@ -77,7 +77,7 @@ static int validate_client(struct intel_guc_client *client,
dev_priv->preempt_context : dev_priv->kernel_context;
if (client->owner != ctx_owner ||
- client->engines != INTEL_INFO(dev_priv)->ring_mask ||
+ client->engines != DEVICE_INFO(dev_priv)->ring_mask ||
client->priority != client_priority ||
client->doorbell_id == GUC_DOORBELL_INVALID)
return -EINVAL;
@@ -263,7 +263,7 @@ static int igt_guc_doorbells(void *arg)
for (i = 0; i < ATTEMPTS; i++) {
clients[i] = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ DEVICE_INFO(dev_priv)->ring_mask,
i % GUC_CLIENT_PRIORITY_NUM,
dev_priv->kernel_context);
A long time ago, maybe in a galaxy far, far away, we introduce INTEL_INFO() with the intent of being able to replace it with the static platform data and let the compiler eliminate all the dead code that wasn't required for the platform. We have been very lax and let ourselves rewrite intel_device_info at runtime, thus losing the static property of INTEL_INFO() and the hopes of DCE. No more! Let's begin the fight back by clearing marking that intel_device_info is static, renaming it intel_device_static_info with the goal of eliminating all mkwrite_intel_info, moving those to a new intel_device_runtime_info. To that end, we also purposefully rename the field and its accessors, forcing existing code to be updated and adapt to the new static/runtime scheme. add/remove: 1/1 grow/shrink: 60/59 up/down: 1028/-3980 (-2952) Function old new delta intel_fbc_update_state_cache.isra - 171 +171 intel_ddi_get_buf_trans_edp 349 444 +95 i915_frequency_info 3203 3274 +71 i915_perf_init 697 767 +70 intel_ddi_get_buf_trans_dp 149 217 +68 intel_power_sequencer_reset 272 314 +42 intel_sprite_plane_format_mod_supported 634 671 +37 intel_gvt_switch_mmio 1925 1954 +29 i915_drpc_info 2199 2226 +27 snb_gt_irq_handler 325 350 +25 get_new_crc_ctl_reg 812 836 +24 intel_runtime_suspend 589 612 +23 intel_can_enable_sagv 470 493 +23 gen5_gt_irq_postinstall 284 307 +23 intel_dsi_init 1306 1326 +20 intel_update_max_cdclk 807 826 +19 skl_atomic_update_crtc_wm 825 843 +18 intel_check_primary_plane 810 827 +17 intel_init_gt_powersave 3077 3091 +14 intel_dsi_get_hw_state 625 639 +14 ilk_wm_get_hw_state 1074 1087 +13 i9xx_set_pipeconf 341 352 +11 intel_check_sprite_plane 2824 2834 +10 ivybridge_parity_work 782 791 +9 i9xx_update_wm 983 992 +9 i915_save_state 598 607 +9 i915_restore_state 618 627 +9 i915_getparam 698 707 +9 intel_compute_dsi_pll 883 891 +8 cmd_handler_mi_display_flip 848 856 +8 intel_vgpu_get_dmabuf 712 719 +7 intel_hdmi_init_connector 1054 1061 +7 i915_gem_userptr_ioctl 722 729 +7 intel_enable_dsi_pll 1060 1066 +6 intel_pipe_config_compare 4794 4799 +5 intel_modeset_init 6158 6163 +5 intel_dsi_post_disable 2760 2765 +5 intel_dp_pps_init 280 285 +5 gen6_rps_idle 202 207 +5 intel_overlay_put_image_ioctl 4982 4986 +4 intel_dsi_reset_clocks 418 422 +4 intel_dp_encoder_reset 364 368 +4 i9xx_update_plane 1325 1329 +4 i9xx_compute_dpll.isra.constprop 271 275 +4 wm_latency_show 232 235 +3 intel_uncore_init 1356 1359 +3 intel_lpe_audio_init 874 877 +3 intel_gvt_init_device 1107 1110 +3 skl_compute_wm 6470 6472 +2 intel_enable_dp 983 985 +2 i9xx_check_plane_surface 217 219 +2 i915_gem_set_caching_ioctl 750 752 +2 i915_disable_vga 118 120 +2 _intel_set_memory_cxsr 793 795 +2 intel_get_gpu_reset 115 116 +1 intel_enable_gt_powersave 6308 6309 +1 intel_dp_voltage_max 108 109 +1 intel_ddi_get_buf_trans_hdmi 131 132 +1 ilk_wm_max_level 51 52 +1 ilk_compute_pipe_wm 1025 1026 +1 clear_intel_crtc_state 718 719 +1 intel_vgpu_init_display 90 89 -1 i915_sr_status 342 341 -1 set_data 118 116 -2 set_clock 112 110 -2 intel_uncore_forcewake_for_reg 745 743 -2 intel_pps_get_registers 332 330 -2 intel_crtc_set_crc_source 485 483 -2 intel_crt_get_modes 137 135 -2 intel_atomic_check 4489 4487 -2 i9xx_hpd_irq_handler 209 207 -2 i915_teardown_sysfs 119 117 -2 i915_gem_init_stolen 1868 1866 -2 i915_drm_suspend_late 233 231 -2 display_crc_ctl_write 1514 1511 -3 csr_load_work_fn 1117 1114 -3 ivb_update_plane 794 790 -4 intel_surf_alignment.isra 154 150 -4 intel_read_wm_latency 707 703 -4 intel_irq_init 1087 1083 -4 intel_infoframe_init 218 214 -4 intel_disable_dsi_pll 268 264 -4 ilk_wm_merge 504 500 -4 intel_atomic_setup_scalers 775 770 -5 edp_notify_handler 215 210 -5 i915_get_crtc_scanoutpos 564 558 -6 i915_driver_load 5052 5046 -6 execlists_init_reg_state.isra 1291 1285 -6 assert_panel_unlocked 334 328 -6 intel_sdvo_get_config 484 477 -7 intel_dp_init_connector 5244 5237 -7 intel_set_cpu_fifo_underrun_reporting 834 826 -8 intel_hdmi_set_gcp_infoframe.isra 410 402 -8 intel_dsi_pre_enable 4564 4556 -8 capture 6168 6160 -8 skl_check_plane_surface 1833 1824 -9 intel_fbc_init 578 569 -9 i9xx_setup_backlight 259 250 -9 intel_modeset_setup_hw_state 3882 3871 -11 cmd_handler_mi_batch_buffer_start 1885 1874 -11 check_for_unclaimed_mmio 231 219 -12 intel_psr_init 605 591 -14 intel_init_pm 1879 1864 -15 dp_aux_ch_ctl_mmio_write 1043 1028 -15 i915_pm_resume_early 390 374 -16 intel_vgpu_decode_primary_plane 1435 1417 -18 intel_init_clock_gating_hooks 483 463 -20 intel_enable_sagv 264 243 -21 intel_disable_sagv 272 251 -21 intel_device_info_runtime_init 2402 2380 -22 __intel_fbc_post_update 1417 1394 -23 intel_PLL_is_valid 212 188 -24 intel_display_print_error_state 895 869 -26 intel_runtime_resume 528 500 -28 intel_init_cdclk_hooks 694 666 -28 ilk_program_watermarks 2090 2056 -34 skl_get_buf_trans_dp 92 - -92 intel_dp_compute_config 2414 2304 -110 intel_fbc_enable 1439 1274 -165 intel_fbc_pre_update 394 209 -185 intel_gvt_setup_mmio_info 46582 43678 -2904 Total: Before=1334171, After=1331219, chg -0.22% Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 20 +-- drivers/gpu/drm/i915/i915_drv.c | 40 ++--- drivers/gpu/drm/i915/i915_drv.h | 130 ++++++++-------- drivers/gpu/drm/i915/i915_gem.c | 6 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 19 +-- drivers/gpu/drm/i915/i915_pci.c | 100 ++++++------ drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 182 +++++++++++----------- drivers/gpu/drm/i915/intel_audio.c | 4 +- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/intel_color.c | 22 +-- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 16 +- drivers/gpu/drm/i915/intel_device_info.h | 10 +- drivers/gpu/drm/i915/intel_display.c | 36 ++--- drivers/gpu/drm/i915/intel_display.h | 10 +- drivers/gpu/drm/i915/intel_dp.c | 4 +- drivers/gpu/drm/i915/intel_engine_cs.c | 12 +- drivers/gpu/drm/i915/intel_fbdev.c | 4 +- drivers/gpu/drm/i915/intel_guc_submission.c | 4 +- drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 14 +- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 2 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 4 +- drivers/gpu/drm/i915/intel_pm.c | 23 +-- drivers/gpu/drm/i915/intel_psr.c | 4 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 10 +- drivers/gpu/drm/i915/selftests/huge_pages.c | 10 +- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/selftests/intel_guc.c | 4 +- 39 files changed, 366 insertions(+), 368 deletions(-)