[v5,4/4] arm64: dts: sdm845: Add serial console support
diff mbox

Message ID 20180222061208.2031-5-rnayak@codeaurora.org
State Under Review
Delegated to: Andy Gross
Headers show

Commit Message

Rajendra Nayak Feb. 22, 2018, 6:12 a.m. UTC
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi    | 39 +++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

Comments

Bjorn Andersson March 4, 2018, 7:59 p.m. UTC | #1
On Wed 21 Feb 22:12 PST 2018, Rajendra Nayak wrote:
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
[..]
> +			qup_uart2: serial@a84000 {
> +				compatible = "qcom,geni-debug-uart";
> +				reg = <0xa84000 0x4000>;
> +				reg-names = "se-phys";
> +				clock-names = "se-clk";

This was changed to "se" in v3 of the GENI patchset, with that this
boots nicely again.

Regards,
Bjorn
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Rajendra Nayak March 5, 2018, 10:43 a.m. UTC | #2
On 03/05/2018 01:29 AM, Bjorn Andersson wrote:
> On Wed 21 Feb 22:12 PST 2018, Rajendra Nayak wrote:
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> [..]
>> +			qup_uart2: serial@a84000 {
>> +				compatible = "qcom,geni-debug-uart";
>> +				reg = <0xa84000 0x4000>;
>> +				reg-names = "se-phys";
>> +				clock-names = "se-clk";
> 
> This was changed to "se" in v3 of the GENI patchset, with that this
> boots nicely again.

Thanks Bjorn for testing.

Karthik, it would be good if you could include just this patch from this series as part
of your GENI series for the next (and subsequent) repost, with updates as needed based on
binding changes?
Karthikeyan Ramasubramanian March 5, 2018, 5:50 p.m. UTC | #3
On 3/5/2018 3:43 AM, Rajendra Nayak wrote:
> 
> 
> On 03/05/2018 01:29 AM, Bjorn Andersson wrote:
>> On Wed 21 Feb 22:12 PST 2018, Rajendra Nayak wrote:
>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> [..]
>>> +			qup_uart2: serial@a84000 {
>>> +				compatible = "qcom,geni-debug-uart";
>>> +				reg = <0xa84000 0x4000>;
>>> +				reg-names = "se-phys";
>>> +				clock-names = "se-clk";
>>
>> This was changed to "se" in v3 of the GENI patchset, with that this
>> boots nicely again.
> 
> Thanks Bjorn for testing.
> 
> Karthik, it would be good if you could include just this patch from this series as part
> of your GENI series for the next (and subsequent) repost, with updates as needed based on
> binding changes?
> 
I will include this patch in my next submission.

Regards,
Karthik.

Patch
diff mbox

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49913f1..2a1ed55b703e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,43 @@ 
 / {
 	model = "Qualcomm Technologies, Inc. SDM845 MTP";
 	compatible = "qcom,sdm845-mtp";
+
+	aliases {
+		serial0 = &qup_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&soc {
+	geni-se@ac0000 {
+		serial@a84000 {
+			status = "okay";
+		};
+	};
+
+	pinctrl@3400000 {
+		qup-uart2-default {
+			pinconf_tx {
+				pins = "gpio4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			pinconf_rx {
+				pins = "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qup-uart2-sleep {
+			pinconf {
+				pins = "gpio4", "gpio5";
+				bias-pull-down;
+			};
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index da3d6ac906c8..0acd6c51115d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@ 
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -195,6 +196,20 @@ 
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+
+			qup_uart2_default: qup-uart2-default {
+				pinmux {
+					function = "qup9";
+					pins = "gpio4", "gpio5";
+				};
+			};
+
+			qup_uart2_sleep: qup-uart2-sleep {
+				pinmux {
+					function = "gpio";
+					pins = "gpio4", "gpio5";
+				};
+			};
 		};
 
 		timer@17c90000 {
@@ -273,5 +288,29 @@ 
 			#interrupt-cells = <4>;
 			cell-index = <0>;
 		};
+
+		geni-se@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0xac0000 0x6000>;
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+
+			qup_uart2: serial@a84000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0xa84000 0x4000>;
+				reg-names = "se-phys";
+				clock-names = "se-clk";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default", "sleep";
+				pinctrl-0 = <&qup_uart2_default>;
+				pinctrl-1 = <&qup_uart2_sleep>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
 	};
 };