| Message ID | 20180222181036.15251-5-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Feb 22, 2018 at 08:10:33PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > While it seems totally unlikely that any system would mix a cpu/north > aux channel with a pch/south port (or vice versa) we should still > consult intel_dp->aux_ch rather than encoder->port when figuring out > which clock is actually used by the aux ch. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pushed to dinq with Chris's irc r-b: 15:07 < vsyrjala> a few trivial patches looking for r-bs: https://patchwork.freedesktop.org/patch/206279/ https://patchwork.freedesktop.org/patch/206280/ 15:41 < ickle> s/_ch/_xfer/ r-b 15:42 < ickle> aux_ch makes sense, but requires some reading for me 16:26 < ickle> vsyrjala: read enough to be happy with AUX_CH_foo, so r-b > --- > drivers/gpu/drm/i915/intel_dp.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 2c3eb90b9499..8d503be73dbd 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -956,8 +956,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) > > static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); > > if (index) > return 0; > @@ -971,8 +970,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > > static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); > > if (index) > return 0; > @@ -982,7 +980,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > * like to run at 2MHz. So, take the cdclk or PCH rawclk value and > * divide by 2000 and use that > */ > - if (intel_dig_port->base.port == PORT_A) > + if (intel_dp->aux_ch == AUX_CH_A) > return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); > else > return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); > @@ -990,10 +988,9 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > > static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); > > - if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { > + if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { > /* Workaround for non-ULT HSW */ > switch (index) { > case 0: return 63; > -- > 2.13.6
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2c3eb90b9499..8d503be73dbd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -956,8 +956,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); if (index) return 0; @@ -971,8 +970,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); if (index) return 0; @@ -982,7 +980,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) * like to run at 2MHz. So, take the cdclk or PCH rawclk value and * divide by 2000 and use that */ - if (intel_dig_port->base.port == PORT_A) + if (intel_dp->aux_ch == AUX_CH_A) return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); else return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); @@ -990,10 +988,9 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); - if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { + if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { /* Workaround for non-ULT HSW */ switch (index) { case 0: return 63;