From patchwork Thu Mar 8 23:46:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10269437 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0A2386016D for ; Thu, 8 Mar 2018 23:47:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F118720415 for ; Thu, 8 Mar 2018 23:47:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E4BD629B17; Thu, 8 Mar 2018 23:47:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6990B20415 for ; Thu, 8 Mar 2018 23:47:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A2FAD6EB6E; Thu, 8 Mar 2018 23:47:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D5AF6EB6D for ; Thu, 8 Mar 2018 23:47:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Mar 2018 15:47:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,443,1515484800"; d="scan'208";a="26448217" Received: from relo-linux-1.fm.intel.com ([10.1.27.112]) by fmsmga002.fm.intel.com with ESMTP; 08 Mar 2018 15:47:00 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Mar 2018 15:46:29 -0800 Message-Id: <20180308234629.27021-3-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308234629.27021-1-daniele.ceraolospurio@intel.com> References: <20180308234629.27021-1-daniele.ceraolospurio@intel.com> Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915: move gen8 irq shifts to intel_lrc.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The only usage outside the intel_lrc.c file is in the ringbuffer init, but the irq mask calculated there is then overwritten for all engines that have a non-zero shift, so we can drop it. This change is not aimed at code saving but at removing from intel_engines information that does not apply to all gens that have the engine. When checking without the temporary WARN_ON, code size is basically unchanged: add/remove: 1/0 grow/shrink: 3/4 up/down: 70/-67 (3) Function old new delta logical_ring_setup 315 343 +28 irq_shifts - 28 +28 intel_init_render_ring_buffer 258 268 +10 reset_common_ring 704 708 +4 intel_engine_init_cmd_parser 1064 1058 -6 intel_engines_init_mmio 1264 1256 -8 intel_ring_default_vfuncs 584 563 -21 intel_engines 224 192 -32 Total: Before=1479719, After=1479722, chg +0.00% Suggested-by: Michel Thierry Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_engine_cs.c | 10 ---------- drivers/gpu/drm/i915/intel_lrc.c | 22 +++++++++++++++++++--- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 - 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a33171d82aee..dbfeff6c46a8 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -92,7 +92,6 @@ struct engine_info { u32 gen : 8; u32 base : 24; } mmio_bases[MAX_MMIO_BASES]; - unsigned irq_shift; }; static const struct engine_info intel_engines[] = { @@ -104,7 +103,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 0, .base = RENDER_RING_BASE } }, - .irq_shift = GEN8_RCS_IRQ_SHIFT, }, [BCS] = { .hw_id = BCS_HW, @@ -114,7 +112,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 6, .base = BLT_RING_BASE } }, - .irq_shift = GEN8_BCS_IRQ_SHIFT, }, [VCS] = { .hw_id = VCS_HW, @@ -126,7 +123,6 @@ static const struct engine_info intel_engines[] = { { .gen = 6, .base = GEN6_BSD_RING_BASE }, { .gen = 4, .base = BSD_RING_BASE } }, - .irq_shift = GEN8_VCS1_IRQ_SHIFT, }, [VCS2] = { .hw_id = VCS2_HW, @@ -137,7 +133,6 @@ static const struct engine_info intel_engines[] = { { .gen = 11, .base = GEN11_BSD2_RING_BASE }, { .gen = 8, .base = GEN8_BSD2_RING_BASE } }, - .irq_shift = GEN8_VCS2_IRQ_SHIFT, }, [VCS3] = { .hw_id = VCS3_HW, @@ -147,7 +142,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_BSD3_RING_BASE } }, - .irq_shift = 0, /* not used */ }, [VCS4] = { .hw_id = VCS4_HW, @@ -157,7 +151,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_BSD4_RING_BASE } }, - .irq_shift = 0, /* not used */ }, [VECS] = { .hw_id = VECS_HW, @@ -168,7 +161,6 @@ static const struct engine_info intel_engines[] = { { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, { .gen = 7, .base = VEBOX_RING_BASE } }, - .irq_shift = GEN8_VECS_IRQ_SHIFT, }, [VECS2] = { .hw_id = VECS2_HW, @@ -178,7 +170,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } }, - .irq_shift = 0, /* not used */ }, }; @@ -298,7 +289,6 @@ intel_engine_setup(struct drm_i915_private *dev_priv, sizeof(engine->name)); engine->hw_id = engine->guc_id = info->hw_id; engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); - engine->irq_shift = info->irq_shift; engine->class = info->class; engine->instance = info->instance; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 999d5f2539d4..1bf8e16d7fa3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1573,6 +1573,14 @@ static u8 gtiir[] = { [VECS] = 3, }; +unsigned int irq_shifts[] = { + [RCS] = GEN8_RCS_IRQ_SHIFT, + [BCS] = GEN8_BCS_IRQ_SHIFT, + [VCS] = GEN8_VCS1_IRQ_SHIFT, + [VCS2] = GEN8_VCS2_IRQ_SHIFT, + [VECS] = GEN8_VECS_IRQ_SHIFT, +}; + static void enable_execlists(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1661,6 +1669,10 @@ static void reset_irq(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int i; + /* TODO: correctly reset irqs for gen11 */ + if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11)) + return; + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); /* @@ -1672,11 +1684,11 @@ static void reset_irq(struct intel_engine_cs *engine) */ for (i = 0; i < 2; i++) { I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), - GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); + GT_CONTEXT_SWITCH_INTERRUPT << irq_shifts[engine->id]); POSTING_READ(GEN8_GT_IIR(gtiir[engine->id])); } GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) & - (GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift)); + (GT_CONTEXT_SWITCH_INTERRUPT << irq_shifts[engine->id])); clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } @@ -2109,7 +2121,11 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) static inline void logical_ring_default_irqs(struct intel_engine_cs *engine) { - unsigned shift = engine->irq_shift; + unsigned shift = 0; + + if (INTEL_GEN(engine->i915) < 11) + shift = irq_shifts[engine->id]; + engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2e4408477ab5..3a7024fdad6f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1943,8 +1943,6 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, static void intel_ring_init_irq(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { - engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; - if (INTEL_GEN(dev_priv) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; @@ -2029,6 +2027,8 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) if (HAS_L3_DPF(dev_priv)) engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; + engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; + if (INTEL_GEN(dev_priv) >= 6) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen7_render_ring_flush; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d8ddea0174ca..08265e312dc2 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -330,7 +330,6 @@ struct intel_engine_cs { u8 instance; u32 context_size; u32 mmio_base; - unsigned int irq_shift; struct intel_ring *buffer; struct intel_timeline *timeline;