From patchwork Tue Mar 13 20:59:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10280793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BFAD66038F for ; Tue, 13 Mar 2018 21:05:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD90F21327 for ; Tue, 13 Mar 2018 21:05:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A01C7284C3; Tue, 13 Mar 2018 21:05:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 85AE621327 for ; Tue, 13 Mar 2018 21:05:32 +0000 (UTC) Received: (qmail 22002 invoked by uid 550); 13 Mar 2018 21:01:24 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 21802 invoked from network); 13 Mar 2018 21:01:10 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c3oPSVAVgFpZKN/1mpdxEhHaxGgyIRs/6tQkwihvkXA=; b=CnoUQUrsK+ZSJfA3h6DSh3lrGEbjVJw5zesP2fQMnNzsMwoXzASnN7nv36zPAejmpp R0Pai2Dl7OaiblftOMPmiq7DR/6oEDSwTY1bvok1eBDoHDSGA2gTm+hxnN/JdHdEccep dc4CZeUt+exZuVqiMC6qvVqRz0Xi1Wp5SUGa3pVhJFT1oSJajEzc7q5KCbq8ePMaDPQY 2GEauqbJse0+apw3gUrHQdiDzduEivnA/U8ompt5qlELkQbUWbD+iN2HZGrMbsRCJwSM bnCqNj47Tjwj72GJ4UJEyu8kqdrkFCmjObxNlq69hTLfkYwUUldoufDURYAaeIixJKzZ guUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c3oPSVAVgFpZKN/1mpdxEhHaxGgyIRs/6tQkwihvkXA=; b=tDpgMTNtPEkomTUD0PdeE510l8CwmLRXwivsxbMn177o3pPybLfZEDDtI7QzxUYr0W xWaF/B45oV/GMHKj43/wm2N2D+jqGUPsFtpLyvhIESZvw583rNz1Vh9kCaMJdH3WicNb s6KoJBh4i+qNsL211PQ/w9MoOCF45nyenVbJvMPLhO5vnXOQH2re7TkfiPFBFnSfwIPj Ot/TuUq+CzlkHlX9q4dEau3x/R1sXl7qy2k6gTy6/kzeZXBvAAOG+bOW+4tOhJXagGny PMqUhGaeJi5GoegPP0pHjOj4eztsUpA/zk6eg+NM9kQ+hRl5NsnkZPVvAeTwHz3gHmbk YwUg== X-Gm-Message-State: AElRT7FNO1v6hnUS+3cdcefCw8TOD9botl2Xo4T2i1uUA+dAZTCD2I9p xkvuC13nfKAAt3bIKYgHMa1fzA== X-Google-Smtp-Source: AG47ELszyghX67BZHlm8pBva/bAoU533tREnYz+DrGciFImvE5egio15X6IPJ9LaM+/kBqFSvxSHBw== X-Received: by 10.101.76.71 with SMTP id l7mr1612139pgr.192.1520974857563; Tue, 13 Mar 2018 14:00:57 -0700 (PDT) From: Thomas Garnier To: Herbert Xu , "David S . Miller" , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Greg Kroah-Hartman , Kate Stewart , Thomas Garnier , Arnd Bergmann , Philippe Ombredanne , Arnaldo Carvalho de Melo , Andrey Ryabinin , Matthias Kaehlcke , Kees Cook , Tom Lendacky , "Kirill A . Shutemov" , Andy Lutomirski , Dominik Brodowski , Borislav Petkov , Borislav Petkov , "Rafael J . Wysocki" , Len Brown , Pavel Machek , Juergen Gross , Alok Kataria , Steven Rostedt , Tejun Heo , Christoph Lameter , Dennis Zhou , Boris Ostrovsky , David Woodhouse , Alexey Dobriyan , "Paul E . McKenney" , Andrew Morton , Nicolas Pitre , Randy Dunlap , "Luis R . Rodriguez" , Christopher Li , Jason Baron , Ashish Kalra , Kyle McMartin , Dou Liyang , Lukas Wunner , Petr Mladek , Sergey Senozhatsky , Masahiro Yamada , Ingo Molnar , Nicholas Piggin , Cao jin , "H . J . Lu" , Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Joerg Roedel , Dave Hansen , Rik van Riel , Jia Zhang , Jiri Slaby , Kyle Huey , Jonathan Corbet , Matthew Wilcox , Michal Hocko , Rob Landley , Baoquan He , Daniel Micay , =?UTF-8?q?Jan=20H=20=2E=20Sch=C3=B6nherr?= Cc: x86@kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xenproject.org, linux-arch@vger.kernel.org, linux-sparse@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, kernel-hardening@lists.openwall.com Subject: [PATCH v2 18/27] xen: Adapt assembly for PIE support Date: Tue, 13 Mar 2018 13:59:36 -0700 Message-Id: <20180313205945.245105-19-thgarnie@google.com> X-Mailer: git-send-email 2.16.2.660.g709887971b-goog In-Reply-To: <20180313205945.245105-1-thgarnie@google.com> References: <20180313205945.245105-1-thgarnie@google.com> X-Virus-Scanned: ClamAV using ClamSMTP Change the assembly code to use the new _ASM_MOVABS macro which get a symbol reference while being PIE compatible. Adapt the relocation tool to ignore 32-bit Xen code. Position Independent Executable (PIE) support will allow to extended the KASLR randomization range below the -2G memory limit. Signed-off-by: Thomas Garnier --- arch/x86/tools/relocs.c | 16 +++++++++++++++- arch/x86/xen/xen-head.S | 11 ++++++----- arch/x86/xen/xen-pvh.S | 13 +++++++++---- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c index a35cc337f883..29283ad3950f 100644 --- a/arch/x86/tools/relocs.c +++ b/arch/x86/tools/relocs.c @@ -832,6 +832,16 @@ static int is_percpu_sym(ElfW(Sym) *sym, const char *symname) strncmp(symname, "init_per_cpu_", 13); } +/* + * Check if the 32-bit relocation is within the xenpvh 32-bit code. + * If so, ignores it. + */ +static int is_in_xenpvh_assembly(ElfW(Addr) offset) +{ + ElfW(Sym) *sym = sym_lookup("pvh_start_xen"); + return sym && (offset >= sym->st_value) && + (offset < (sym->st_value + sym->st_size)); +} static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, const char *symname) @@ -895,8 +905,12 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, * the relocations are processed. * Make sure that the offset will fit. */ - if (r_type != R_X86_64_64 && (int32_t)offset != (int64_t)offset) + if (r_type != R_X86_64_64 && + (int32_t)offset != (int64_t)offset) { + if (is_in_xenpvh_assembly(offset)) + break; die("Relocation offset doesn't fit in 32 bits\n"); + } if (r_type == R_X86_64_64) add_reloc(&relocs64, offset); diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 96f26e026783..210568e63c84 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -28,14 +28,15 @@ ENTRY(startup_xen) /* Clear .bss */ xor %eax,%eax - mov $__bss_start, %_ASM_DI - mov $__bss_stop, %_ASM_CX + _ASM_MOVABS $__bss_start, %_ASM_DI + _ASM_MOVABS $__bss_stop, %_ASM_CX sub %_ASM_DI, %_ASM_CX shr $__ASM_SEL(2, 3), %_ASM_CX rep __ASM_SIZE(stos) - mov %_ASM_SI, xen_start_info - mov $init_thread_union+THREAD_SIZE, %_ASM_SP + _ASM_MOVABS $xen_start_info, %_ASM_AX + _ASM_MOV %_ASM_SI, (%_ASM_AX) + _ASM_MOVABS $init_thread_union+THREAD_SIZE, %_ASM_SP #ifdef CONFIG_X86_64 /* Set up %gs. @@ -46,7 +47,7 @@ ENTRY(startup_xen) * init data section till per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movq $INIT_PER_CPU_VAR(irq_stack_union),%rax + movabsq $INIT_PER_CPU_VAR(irq_stack_union),%rax cdq wrmsr #endif diff --git a/arch/x86/xen/xen-pvh.S b/arch/x86/xen/xen-pvh.S index e1a5fbeae08d..43e234c7c2de 100644 --- a/arch/x86/xen/xen-pvh.S +++ b/arch/x86/xen/xen-pvh.S @@ -101,8 +101,8 @@ ENTRY(pvh_start_xen) call xen_prepare_pvh /* startup_64 expects boot_params in %rsi. */ - mov $_pa(pvh_bootparams), %rsi - mov $_pa(startup_64), %rax + movabs $_pa(pvh_bootparams), %rsi + movabs $_pa(startup_64), %rax jmp *%rax #else /* CONFIG_X86_64 */ @@ -137,10 +137,15 @@ END(pvh_start_xen) .section ".init.data","aw" .balign 8 + /* + * Use a quad for _pa(gdt_start) because PIE does not understand a + * long is enough. The resulting value will still be in the lower long + * part. + */ gdt: .word gdt_end - gdt_start - .long _pa(gdt_start) - .word 0 + .quad _pa(gdt_start) + .balign 8 gdt_start: .quad 0x0000000000000000 /* NULL descriptor */ .quad 0x0000000000000000 /* reserved */