From patchwork Wed Apr 11 17:57:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vathsala nagaraju X-Patchwork-Id: 10335941 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 216906053B for ; Wed, 11 Apr 2018 17:57:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 115D427D4A for ; Wed, 11 Apr 2018 17:57:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 05E5727E5A; Wed, 11 Apr 2018 17:57:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5B5F927D4A for ; Wed, 11 Apr 2018 17:57:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5123F6E6B0; Wed, 11 Apr 2018 17:57:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id E2A156E6B0 for ; Wed, 11 Apr 2018 17:57:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Apr 2018 10:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,437,1517904000"; d="scan'208";a="32629259" Received: from vnagaraj-hp-elitedesk-800-g1-twr.iind.intel.com ([10.66.247.146]) by orsmga007.jf.intel.com with ESMTP; 11 Apr 2018 10:57:03 -0700 From: vathsala nagaraju To: rodrigo.vivi@intel.com, intel-gfx@lists.freedesktop.org Date: Wed, 11 Apr 2018 23:27:01 +0530 Message-Id: <1523469421-21131-1-git-send-email-vathsala.nagaraju@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Puthikorn Voravootivat , Maulik V Vaghela MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Vathsala Nagaraju For psr block #9, the vbt description has moved to options [0-3] for TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt structure. Since spec does not mention from which VBT version this change was added to vbt.bsf file, we cannot depend on bdb->version check to change for all the platforms. There is RCR inplace for GOP team to provide the version number to make generic change. Since Kabylake with bdb version 209 is having this change, limiting this change to kbl and version 209+ to unblock google. bspec 20131 v2: (Jani and Rodrigo) move the 165 version check to intel_bios.c Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Signed-off-by: Maulik V Vaghela Signed-off-by: Vathsala Nagaraju --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 3 ++ drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++++++++------------- 3 files changed, 61 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5373b17..6aa6d68 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1075,6 +1075,7 @@ struct intel_vbt_data { enum psr_lines_to_wait lines_to_wait; int tp1_wakeup_time; int tp2_tp3_wakeup_time; + int is_tp_time_options; } psr; struct { diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c5c7530..08e82e0 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -659,6 +659,9 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, return; } + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) + dev_priv->vbt.psr.is_tp_time_options = true; + psr_table = &psr->psr_table[panel_type]; dev_priv->vbt.psr.full_link = psr_table->full_link; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2d53f73..74ed6d0 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (dev_priv->psr.link_standby) val |= EDP_PSR_LINK_STANDBY; - if (dev_priv->vbt.psr.tp1_wakeup_time > 5) - val |= EDP_PSR_TP1_TIME_2500us; - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) - val |= EDP_PSR_TP1_TIME_500us; - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) - val |= EDP_PSR_TP1_TIME_100us; - else - val |= EDP_PSR_TP1_TIME_0us; - - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) - val |= EDP_PSR_TP2_TP3_TIME_2500us; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) - val |= EDP_PSR_TP2_TP3_TIME_500us; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) - val |= EDP_PSR_TP2_TP3_TIME_100us; - else - val |= EDP_PSR_TP2_TP3_TIME_0us; + if (dev_priv->vbt.psr.is_tp_time_options) { + if (dev_priv->vbt.psr.tp1_wakeup_time == 0) + val |= EDP_PSR_TP1_TIME_500us; + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1) + val |= EDP_PSR_TP1_TIME_100us; + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2) + val |= EDP_PSR_TP1_TIME_2500us; + else + val |= EDP_PSR_TP1_TIME_0us; + } else { + if (dev_priv->vbt.psr.tp1_wakeup_time > 5) + val |= EDP_PSR_TP1_TIME_2500us; + else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) + val |= EDP_PSR_TP1_TIME_500us; + else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) + val |= EDP_PSR_TP1_TIME_100us; + else + val |= EDP_PSR_TP1_TIME_0us; + } + if (dev_priv->vbt.psr.is_tp_time_options) { + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) + val |= EDP_PSR_TP2_TP3_TIME_500us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) + val |= EDP_PSR_TP2_TP3_TIME_100us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) + val |= EDP_PSR_TP2_TP3_TIME_2500us; + else + val |= EDP_PSR_TP2_TP3_TIME_0us; + } else { + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) + val |= EDP_PSR_TP2_TP3_TIME_2500us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) + val |= EDP_PSR_TP2_TP3_TIME_500us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) + val |= EDP_PSR_TP2_TP3_TIME_100us; + else + val |= EDP_PSR_TP2_TP3_TIME_0us; + } if (intel_dp_source_supports_hbr2(intel_dp) && drm_dp_tps3_supported(intel_dp->dpcd)) val |= EDP_PSR_TP1_TP3_SEL; @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) } val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); - - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) - val |= EDP_PSR2_TP2_TIME_2500; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) - val |= EDP_PSR2_TP2_TIME_500; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) - val |= EDP_PSR2_TP2_TIME_100; - else - val |= EDP_PSR2_TP2_TIME_50; - + if (dev_priv->vbt.psr.is_tp_time_options) { + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) + val |= EDP_PSR2_TP2_TIME_500; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) + val |= EDP_PSR2_TP2_TIME_100; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) + val |= EDP_PSR2_TP2_TIME_2500; + else + val |= EDP_PSR2_TP2_TIME_50; + } else { + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) + val |= EDP_PSR2_TP2_TIME_2500; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) + val |= EDP_PSR2_TP2_TIME_500; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) + val |= EDP_PSR2_TP2_TIME_100; + else + val |= EDP_PSR2_TP2_TIME_50; + } I915_WRITE(EDP_PSR2_CTL, val); }