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Tue, 17 Apr 2018 12:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523966838; bh=Cg87gi6P0LUYKco/LN8ojONKQqGSlyI0SWmNUfmkANs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cOmXoApn2iYVnMEhhNlocQstI4CkVTJiBg7/yCazSoIQQ0r2ITyv2QpOb9xHcgRBN NZyrooEETgGEW7ytw+5EQeyZ1VcTbm3ST8wiS39AKtGn6RwLdQIm6CqWwkNuFHS/6b ZyrbLgiFxK21a0f7tJ6P1FF1bm3HPSna16rhH3/4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 05EF5601E8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=pillair@codeaurora.org From: pillair@codeaurora.org To: ath10k@lists.infradead.org Subject: [PATCH v2 1/4] ath10k: Add hw params for shadow register support Date: Tue, 17 Apr 2018 17:36:58 +0530 Message-Id: <1523966821-21903-2-git-send-email-pillair@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523966821-21903-1-git-send-email-pillair@codeaurora.org> References: <1523966821-21903-1-git-send-email-pillair@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180417_050723_770002_7471F35D X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: ath10k@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rakesh Pillai , linux-wireless@vger.kernel.org MIME-Version: 1.0 Sender: "ath10k" Errors-To: ath10k-bounces+patchwork-ath10k=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rakesh Pillai wcn3990 supports shadow register for ce write. Add a hw param for shadow register support. Signed-off-by: Rakesh Pillai --- drivers/net/wireless/ath/ath10k/core.c | 14 ++++++++++++++ drivers/net/wireless/ath/ath10k/hw.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c index 64479acd9dc5..5a9d222acfe6 100644 --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c @@ -90,6 +90,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .num_wds_entries = 0x20, .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, + .shadow_reg_support = false, }, { .id = QCA988X_HW_2_0_VERSION, @@ -120,6 +121,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA9887_HW_1_0_VERSION, @@ -150,6 +152,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA6174_HW_2_1_VERSION, @@ -179,6 +182,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA6174_HW_2_1_VERSION, @@ -208,6 +212,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA6174_HW_3_0_VERSION, @@ -237,6 +242,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA6174_HW_3_2_VERSION, @@ -269,6 +275,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA99X0_HW_2_0_DEV_VERSION, @@ -304,6 +311,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA9984_HW_1_0_DEV_VERSION, @@ -344,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA9888_HW_2_0_DEV_VERSION, @@ -383,6 +392,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA9377_HW_1_0_DEV_VERSION, @@ -412,6 +422,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA9377_HW_1_1_DEV_VERSION, @@ -443,6 +454,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = QCA4019_HW_1_0_DEV_VERSION, @@ -479,6 +491,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = false, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .per_ce_irq = false, + .shadow_reg_support = false, }, { .id = WCN3990_HW_1_0_DEV_VERSION, @@ -500,6 +513,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { .target_64bit = true, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, .per_ce_irq = true, + .shadow_reg_support = true, }, }; diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h index 3041eba61e54..74faee5a2578 100644 --- a/drivers/net/wireless/ath/ath10k/hw.h +++ b/drivers/net/wireless/ath/ath10k/hw.h @@ -1,6 +1,7 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. + * Copyright (c) 2018 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -571,6 +572,9 @@ struct ath10k_hw_params { /* target supporting per ce IRQ */ bool per_ce_irq; + + /* target supporting shadow register for ce write */ + bool shadow_reg_support; }; struct htt_rx_desc;