@@ -15,6 +15,7 @@
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
@@ -791,7 +792,7 @@ static const struct mtk_gate_regs mm1_cg_regs __initconst = {
.ops = &mtk_clk_gate_ops_setclr, \
}
-static const struct mtk_gate mm_clks[] __initconst = {
+static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
@@ -1152,10 +1153,13 @@ static void __init mtk_imgsys_init(struct device_node *node)
}
CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
-static void __init mtk_mmsys_init(struct device_node *node)
+static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
int r;
+ struct device_node *node;
+
+ node = pdev->dev.parent->of_node;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@@ -1166,8 +1170,17 @@ static void __init mtk_mmsys_init(struct device_node *node)
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
+
+ return r;
}
-CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
+
+static struct platform_driver clk_mt8173_mm_drv = {
+ .probe = mtk_mmsys_probe,
+ .driver = {
+ .name = "clk-mt8173-mm",
+ },
+};
+builtin_platform_driver(clk_mt8173_mm_drv);
static void __init mtk_vdecsys_init(struct device_node *node)
{