Questions about bringing up MT7623 board

Commit Message

Kristian Evensen April 30, 2018, 4:12 p.m. UTC

Hi Ryder,

On Mon, Apr 30, 2018 at 3:42 AM, Ryder Lee <[e-mail]> wrote:
> We didn't support port2 (pcie@2,0) for mainline version, but if you want
> to use it you could take a look at -
> https://patchwork.kernel.org/patch/9747713/
>
> grep: HIF_SYSCFG1 /HIF_SYSCFG1_PHY2_MASK
>
> That is, you need to clear these bits to 0 to enable PHY for pcie@2,0.

Thanks a lot for the pointer. With the attached patch and a slight
update to my DTS (add a reference to hifsys for usb3phy2), both the
PCIe-slots work and I have both 2.4Ghz and 5GHz.

The "only" thing left now is the USB OTG-port. I got the SDK from the
vendor yesterday, but without any proper documentation. Looking
through the kernel configuration for my board, the only relevant
select options (that I could find), was that USB_MUSB_HDRC and
MUSB_PIO_ONLY was enabled. Enabling those options for my 4.14 kernel
has seemingly no effect, the modem connected to PCIe-slot connected to
the OTG-port (puh) is not visible. Does anyone know where I should
start looking in order to enable this port? I see that there is some
mention of OTG in phy-mtk-tphy.c, but not sure if that is relevant.
Also, as far as I can tell, my device should be set to host mode and
both usb-phys are activated (phy1 is the port on the front of my
board, phy2 shared with pcie).

Thanks in advance for any help (again)!

BR,
Kristian

Patch

From 4d054fa1f72c65e9640b3dd1a90c2ecb6dd57445 Mon Sep 17 00:00:00 2001
From: Kristian Evensen <[e-mail]>
Date: Mon, 30 Apr 2018 14:38:01 +0200
Subject: [PATCH] Add hifsys-support to phy-mtk-tphy

---
 drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 721a2a1c9..0cb1cea53 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -22,6 +22,8 @@ 
 #include <linux/of_address.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 /* version V1 sub-banks offset base address */
 /* banks shared by multiple phys */
@@ -259,6 +261,9 @@ 
 #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
 #define RG_CDR_BIRLTD0_GEN3_VAL(x)	(0x1f & (x))
 
+#define HIF_SYSCFG1			0x14
+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
+
 enum mtk_phy_version {
 	MTK_PHY_V1 = 1,
 	MTK_PHY_V2,
@@ -302,6 +307,7 @@  struct mtk_tphy {
 	struct clk *u3phya_ref;	/* reference clock of usb3 anolog phy */
 	const struct mtk_phy_pdata *pdata;
 	struct mtk_phy_instance **phys;
+	struct regmap *hif;
 	int nphys;
 };
 
@@ -594,6 +600,10 @@  static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 	if (tphy->pdata->version != MTK_PHY_V1)
 		return;
 
+	if (tphy->hif)
+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
+				   HIF_SYSCFG1_PHY2_MASK, 0);
+
 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
@@ -1008,6 +1018,16 @@  static int mtk_tphy_probe(struct platform_device *pdev)
 		tphy->u3phya_ref = NULL;
 	}
 
+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
+							    "mediatek,phy-switch");
+		if (IS_ERR(tphy->hif)) {
+			dev_err(&pdev->dev,
+				"missing \"mediatek,phy-switch\" phandle\n");
+			return PTR_ERR(tphy->hif);
+		}
+	}
+
 	port = 0;
 	for_each_child_of_node(np, child_np) {
 		struct mtk_phy_instance *instance;
-- 
2.14.1