| Message ID | 54dbd1d2-8279-5073-cffb-c647fba91e42@cogentembedded.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Sergei, On Tue, May 8, 2018 at 6:39 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the device node for the second Cortex-A53 CPU core. > > Based on the original (and large) patch by Daisuke Matsushita > <daisuke.matsushita.ns@hitachi.com>. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Dupe of https://patchwork.kernel.org/patch/10032875/ From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support" (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html) > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi > @@ -41,6 +41,16 @@ > enable-method = "psci"; > }; > > + a53_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; Missing space after the comma. Gr{oetje,eeting}s, Geert
On 05/08/2018 09:40 PM, Geert Uytterhoeven wrote: >> Add the device node for the second Cortex-A53 CPU core. >> >> Based on the original (and large) patch by Daisuke Matsushita >> <daisuke.matsushita.ns@hitachi.com>. >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Dupe of https://patchwork.kernel.org/patch/10032875/ Sorry! Not an exact dupe, though -- mine has clock/power #define's used, yours -- only bare #s. :-) > From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support" > (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html) Hmm... what's the fate of this series? >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi >> @@ -41,6 +41,16 @@ >> enable-method = "psci"; >> }; >> >> + a53_1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53","arm,armv8"; > > Missing space after the comma. Oops. :-) > Gr{oetje,eeting}s, > > Geert MBR, Sergei
On Tue, May 08, 2018 at 09:47:10PM +0300, Sergei Shtylyov wrote: > On 05/08/2018 09:40 PM, Geert Uytterhoeven wrote: > > >> Add the device node for the second Cortex-A53 CPU core. > >> > >> Based on the original (and large) patch by Daisuke Matsushita > >> <daisuke.matsushita.ns@hitachi.com>. > >> > >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > > Dupe of https://patchwork.kernel.org/patch/10032875/ > > Sorry! > Not an exact dupe, though -- mine has clock/power #define's used, > yours -- only bare #s. :-) > > > From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support" > > (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html) > > Hmm... what's the fate of this series? There is now a v2 of Geert's series which incorporates your enhancements. I will apply that.
Hello! On 05/09/2018 10:05 PM, Simon Horman wrote: >>>> Add the device node for the second Cortex-A53 CPU core. >>>> >>>> Based on the original (and large) patch by Daisuke Matsushita >>>> <daisuke.matsushita.ns@hitachi.com>. >>>> >>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>> >>> Dupe of https://patchwork.kernel.org/patch/10032875/ >> >> Sorry! >> Not an exact dupe, though -- mine has clock/power #define's used, >> yours -- only bare #s. :-) >> >>> From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support" >>> (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html) >> >> Hmm... what's the fate of this series? > > There is now a v2 of Geert's series which incorporates your enhancements. I suggested to respin it. :-) > I will apply that. Thank you. For the record, I had better luck than Geert testing SMP on Eagle: only CPU0 couldn't be offlined (and I was unable to find a workaround), others could be on/ offlined w/o issues. As for suspend/resume -- it did work but I could only test s2idle (/sys/power/mem_sleep had no other variants)... MBR, Sergei
On Thu, May 10, 2018 at 07:43:03PM +0300, Sergei Shtylyov wrote: > Hello! > > On 05/09/2018 10:05 PM, Simon Horman wrote: > > >>>> Add the device node for the second Cortex-A53 CPU core. > >>>> > >>>> Based on the original (and large) patch by Daisuke Matsushita > >>>> <daisuke.matsushita.ns@hitachi.com>. > >>>> > >>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > >>> > >>> Dupe of https://patchwork.kernel.org/patch/10032875/ > >> > >> Sorry! > >> Not an exact dupe, though -- mine has clock/power #define's used, > >> yours -- only bare #s. :-) > >> > >>> From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support" > >>> (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html) > >> > >> Hmm... what's the fate of this series? > > > > There is now a v2 of Geert's series which incorporates your enhancements. > > I suggested to respin it. :-) Thanks, that would have been my suggestion too :) > > I will apply that. > > Thank you. > For the record, I had better luck than Geert testing SMP on Eagle: > only CPU0 couldn't be offlined (and I was unable to find a > workaround), others could be on/ offlined w/o issues. As for > suspend/resume -- it did work but I could only test s2idle > (/sys/power/mem_sleep had no other variants)... Thanks. Perhaps you have a more recent firmware than Geert. I would expect the CPU0 issue you describe will be resolved in time in the firmware.
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -41,6 +41,16 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; + power-domains = <&sysc R8A77970_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc R8A77970_PD_CA53_SCU>;