| Message ID | 1526667193-9471-1-git-send-email-yunwei.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 5/18/2018 11:13 AM, Yunwei Zhang wrote: > WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as > well. > > References: HSD#1405586840, BSID#0575 > > Cc: Oscar Mateo <oscar.mateo@intel.com> > Cc: Michel Thierry <michel.thierry@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/intel_workarounds.c | 5 ++++- > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 511975f..9ce4dd6 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -829,7 +829,7 @@ u32 intel_calculate_s_ss_select(struct drm_i915_private *dev_priv) > > mcr_s_ss_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; > > - if (INTEL_GEN(dev_priv) == 10) > + if (INTEL_GEN(dev_priv) >= 10) > mcr_s_ss_select = GEN8_MCR_SLICE(slice) | > GEN8_MCR_SUBSLICE(subslice); Wait, shouldn't these be GEN11_MCR_SLICE() and GEN11_MCR_SUBSLICE() in the case of ICL? > else > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index d814368..bbf3de5 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -686,7 +686,7 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv) > mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK | > GEN8_MCR_SUBSLICE_MASK; > /* > - * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl > + * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl > * Before any MMIO read into slice/subslice specific registers, MCR > * packet control register needs to be programmed to point to any > * enabled s/ss pair. Otherwise, incorrect values will be returned. > @@ -724,6 +724,9 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv) > > static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) > { > + /* WaProgramMgsrForCorrectSliceSpecificMmioReads: icl */ > + wa_init_mcr(dev_priv); > + > /* This is not an Wa. Enable for better image quality */ > I915_WRITE(_3D_CHICKEN3, > _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 511975f..9ce4dd6 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -829,7 +829,7 @@ u32 intel_calculate_s_ss_select(struct drm_i915_private *dev_priv) mcr_s_ss_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; - if (INTEL_GEN(dev_priv) == 10) + if (INTEL_GEN(dev_priv) >= 10) mcr_s_ss_select = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); else diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index d814368..bbf3de5 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -686,7 +686,7 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv) mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; /* - * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl + * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl * Before any MMIO read into slice/subslice specific registers, MCR * packet control register needs to be programmed to point to any * enabled s/ss pair. Otherwise, incorrect values will be returned. @@ -724,6 +724,9 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv) static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) { + /* WaProgramMgsrForCorrectSliceSpecificMmioReads: icl */ + wa_init_mcr(dev_priv); + /* This is not an Wa. Enable for better image quality */ I915_WRITE(_3D_CHICKEN3, _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as well. References: HSD#1405586840, BSID#0575 Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_workarounds.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-)