| Message ID | 20180522002558.29262-13-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu: > From: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > > Start using the new registers for ICL and on. I previously put this patch in a series that did not make use of cnl_calc_wrpll_link() for ICL yet. This series makes ICL run cnl_calc_wrpll_link(), so this patch makes sense now. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 0d8bed8e2200..32e7482b64dd 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1381,8 +1381,13 @@ static int cnl_calc_wrpll_link(struct > drm_i915_private *dev_priv, > uint32_t cfgcr0, cfgcr1; > uint32_t p0, p1, p2, dco_freq, ref_clock; > > - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); > - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); > + if (INTEL_GEN(dev_priv) >= 11) { > + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); > + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); > + } else { > + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); > + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); > + } > > p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; > p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0d8bed8e2200..32e7482b64dd 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1381,8 +1381,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, uint32_t cfgcr0, cfgcr1; uint32_t p0, p1, p2, dco_freq, ref_clock; - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); + if (INTEL_GEN(dev_priv) >= 11) { + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); + } else { + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); + } p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;