| Message ID | 1527154169-32380-4-git-send-email-michel.pollet@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Hi Michel, On Thu, May 24, 2018 at 11:28 AM, Michel Pollet <michel.pollet@bp.renesas.com> wrote: > This adds the Renesas R9A06G032 bare bone support. > > This currently only handles generic parts (gic, architected timer) > and a UART. > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + ranges; > + > + sysctrl: sysctrl@4000c000 { system-controller@ > + compatible = "renesas,r9a06g032-sysctrl"; > + reg = <0x4000c000 0x1000>; > + status = "okay"; > + #clock-cells = <1>; > + }; With the minor nit above resolved, and pending acceptance of the sysctrl bindings: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
On Fri, May 25, 2018 at 11:27:46AM +0200, Geert Uytterhoeven wrote: > Hi Michel, > > On Thu, May 24, 2018 at 11:28 AM, Michel Pollet > <michel.pollet@bp.renesas.com> wrote: > > This adds the Renesas R9A06G032 bare bone support. > > > > This currently only handles generic parts (gic, architected timer) > > and a UART. > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + interrupt-parent = <&gic>; > > + ranges; > > + > > + sysctrl: sysctrl@4000c000 { > > system-controller@ > > > + compatible = "renesas,r9a06g032-sysctrl"; > > + reg = <0x4000c000 0x1000>; > > + status = "okay"; > > + #clock-cells = <1>; > > + }; > > With the minor nit above resolved, and pending acceptance of the > sysctrl bindings: > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks. I have marked this patch, and the following one, as deferred pending acceptance of those bindings. Please repost or otherwise ping me once that has happened. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi new file mode 100644 index 0000000..9534f1b --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a06g032-sysctrl.h> + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl R9A06G032_DIV_CA7>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl R9A06G032_DIV_CA7>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + sysctrl: sysctrl@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + }; + + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>; + clock-names = "baudclk"; + status = "disabled"; + }; + + gic: gic@44101000 { + compatible = "arm,cortex-a7-gic", "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + timer { + compatible = "arm,cortex-a7-timer", + "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +};
This adds the Renesas R9A06G032 bare bone support. This currently only handles generic parts (gic, architected timer) and a UART. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi