| Message ID | 1528973829-25493-3-git-send-email-michel.pollet@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
On Thu, Jun 14, 2018 at 11:56:31AM +0100, Michel Pollet wrote: > The Renesas R9A06G032 SYSCTRL node description. > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > --- > .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt One nit, otherwise: Reviewed-by: Rob Herring <robh@kernel.org> > > diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > new file mode 100644 > index 0000000..f6cb5e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > @@ -0,0 +1,44 @@ > +* Renesas R9A06G032 SYSCTRL > + > +Required Properties: > + > + - compatible: Must be: > + - "renesas,r9a06g032-sysctrl" > + - reg: Base address and length of the SYSCTRL IO block. > + - #clock-cells: Must be 1 > + - clocks: References to the parent clocks: > + - external 40mhz crystal. > + - external (optional) 32.768khz > + - external (optional) jtag input > + - external (optional) RGMII_REFCLK > + - clock-names: Must be: > + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; > + > +Examples > +-------- > + > + - SYSCTRL node: > + > + sysctrl: system-controller@4000c000 { > + compatible = "renesas,r9a06g032-sysctrl"; > + reg = <0x4000c000 0x1000>; > + status = "okay"; Don't show status in examples. > + #clock-cells = <1>; > + > + clocks = <&ext_mclk>, <&ext_rtc_clk>, > + <&ext_jtag_clk>, <&ext_rgmii_ref>; > + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; > + }; > + > + - Other nodes can use the clocks provided by SYSCTRL as in: > + > + #include <dt-bindings/clock/r9a06g032-sysctrl.h> > + uart0: serial@40060000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x40060000 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&sysctrl R9A06G032_CLK_UART0>; > + clock-names = "baudclk"; > + }; > -- > 2.7.4 >
On Wed, Jun 20, 2018 at 5:43 PM Rob Herring <robh@kernel.org> wrote: > On Thu, Jun 14, 2018 at 11:56:31AM +0100, Michel Pollet wrote: > > The Renesas R9A06G032 SYSCTRL node description. > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > --- > > .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 44 ++++++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > > One nit, otherwise: > > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > > +Examples > > +-------- > > + > > + - SYSCTRL node: > > + > > + sysctrl: system-controller@4000c000 { > > + compatible = "renesas,r9a06g032-sysctrl"; > > + reg = <0x4000c000 0x1000>; > > + status = "okay"; > > Don't show status in examples. Thanks, queuing in clk-renesas-for-v4.19 with the above fixed. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt new file mode 100644 index 0000000..f6cb5e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt @@ -0,0 +1,44 @@ +* Renesas R9A06G032 SYSCTRL + +Required Properties: + + - compatible: Must be: + - "renesas,r9a06g032-sysctrl" + - reg: Base address and length of the SYSCTRL IO block. + - #clock-cells: Must be 1 + - clocks: References to the parent clocks: + - external 40mhz crystal. + - external (optional) 32.768khz + - external (optional) jtag input + - external (optional) RGMII_REFCLK + - clock-names: Must be: + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + +Examples +-------- + + - SYSCTRL node: + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + }; + + - Other nodes can use the clocks provided by SYSCTRL as in: + + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>; + clock-names = "baudclk"; + };
The Renesas R9A06G032 SYSCTRL node description. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> --- .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt