[libdrm,2/2] intel: Introducing Amber Lake platform
diff mbox

Message ID 20180619234521.20713-2-jose.souza@intel.com
State New
Headers show

Commit Message

José Roberto de Souza June 19, 2018, 11:45 p.m. UTC
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that now is
moved to AML page.

So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it will be handled as a KBL.

This is a copy of merged i915's
commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 intel/intel_chipset.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Rodrigo Vivi June 20, 2018, 11:31 p.m. UTC | #1
On Tue, Jun 19, 2018 at 04:45:21PM -0700, José Roberto de Souza wrote:
> Amber Lake uses the same gen graphics as Kaby Lake, including a id
> that were previously marked as reserved on Kaby Lake, but that now is
> moved to AML page.
> 
> So, let's just move it to AML macro that will feed into KBL macro
> just to keep it better organized to make easier future code review
> but it will be handled as a KBL.
> 
> This is a copy of merged i915's
> commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I just didn't push yet because I haven't migrated my system to
new gitlab yet. And I wasn't able to login.
I hope that someone else can push these 2 patches for now.
I will try to get my gitlab account working later anyways...

Thanks,
Rodrigo.

> ---
>  intel/intel_chipset.h | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 44e65f9e..583d6447 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -201,7 +201,6 @@
>  #define PCI_CHIP_KABYLAKE_ULX_GT1_5	0x5915
>  #define PCI_CHIP_KABYLAKE_ULX_GT1	0x590E
>  #define PCI_CHIP_KABYLAKE_ULX_GT2_0	0x591E
> -#define PCI_CHIP_KABYLAKE_ULX_GT2_1	0x591C
>  #define PCI_CHIP_KABYLAKE_DT_GT2	0x5912
>  #define PCI_CHIP_KABYLAKE_M_GT2		0x5917
>  #define PCI_CHIP_KABYLAKE_DT_GT1	0x5902
> @@ -213,6 +212,9 @@
>  #define PCI_CHIP_KABYLAKE_SRV_GT1	0x590A
>  #define PCI_CHIP_KABYLAKE_WKS_GT2	0x591D
>  
> +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1	0x591C
> +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2	0x87C0
> +
>  #define PCI_CHIP_BROXTON_0		0x0A84
>  #define PCI_CHIP_BROXTON_1		0x1A84
>  #define PCI_CHIP_BROXTON_2		0x5A84
> @@ -468,12 +470,13 @@
>  #define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0	|| \
> -				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_M_GT2	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2	|| \
> -				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
> +				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
> +				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1	|| \
> +				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
>  
>  #define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0	|| \
>  				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1	|| \
> -- 
> 2.17.1
>
Rodrigo Vivi June 20, 2018, 11:42 p.m. UTC | #2
On Wed, Jun 20, 2018 at 04:31:15PM -0700, Rodrigo Vivi wrote:
> On Tue, Jun 19, 2018 at 04:45:21PM -0700, José Roberto de Souza wrote:
> > Amber Lake uses the same gen graphics as Kaby Lake, including a id
> > that were previously marked as reserved on Kaby Lake, but that now is
> > moved to AML page.
> > 
> > So, let's just move it to AML macro that will feed into KBL macro
> > just to keep it better organized to make easier future code review
> > but it will be handled as a KBL.
> > 
> > This is a copy of merged i915's
> > commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> I just didn't push yet because I haven't migrated my system to
> new gitlab yet. And I wasn't able to login.
> I hope that someone else can push these 2 patches for now.
> I will try to get my gitlab account working later anyways...

nevermind. the reset pswd email finally arrived on my inbox
so gitlab up and running

patches pushed, thanks.

> 
> Thanks,
> Rodrigo.
> 
> > ---
> >  intel/intel_chipset.h | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> > index 44e65f9e..583d6447 100644
> > --- a/intel/intel_chipset.h
> > +++ b/intel/intel_chipset.h
> > @@ -201,7 +201,6 @@
> >  #define PCI_CHIP_KABYLAKE_ULX_GT1_5	0x5915
> >  #define PCI_CHIP_KABYLAKE_ULX_GT1	0x590E
> >  #define PCI_CHIP_KABYLAKE_ULX_GT2_0	0x591E
> > -#define PCI_CHIP_KABYLAKE_ULX_GT2_1	0x591C
> >  #define PCI_CHIP_KABYLAKE_DT_GT2	0x5912
> >  #define PCI_CHIP_KABYLAKE_M_GT2		0x5917
> >  #define PCI_CHIP_KABYLAKE_DT_GT1	0x5902
> > @@ -213,6 +212,9 @@
> >  #define PCI_CHIP_KABYLAKE_SRV_GT1	0x590A
> >  #define PCI_CHIP_KABYLAKE_WKS_GT2	0x591D
> >  
> > +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1	0x591C
> > +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2	0x87C0
> > +
> >  #define PCI_CHIP_BROXTON_0		0x0A84
> >  #define PCI_CHIP_BROXTON_1		0x1A84
> >  #define PCI_CHIP_BROXTON_2		0x5A84
> > @@ -468,12 +470,13 @@
> >  #define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0	|| \
> > -				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_M_GT2	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2	|| \
> > -				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
> > +				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
> > +				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1	|| \
> > +				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
> >  
> >  #define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0	|| \
> >  				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1	|| \
> > -- 
> > 2.17.1
> >

Patch
diff mbox

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 44e65f9e..583d6447 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -201,7 +201,6 @@ 
 #define PCI_CHIP_KABYLAKE_ULX_GT1_5	0x5915
 #define PCI_CHIP_KABYLAKE_ULX_GT1	0x590E
 #define PCI_CHIP_KABYLAKE_ULX_GT2_0	0x591E
-#define PCI_CHIP_KABYLAKE_ULX_GT2_1	0x591C
 #define PCI_CHIP_KABYLAKE_DT_GT2	0x5912
 #define PCI_CHIP_KABYLAKE_M_GT2		0x5917
 #define PCI_CHIP_KABYLAKE_DT_GT1	0x5902
@@ -213,6 +212,9 @@ 
 #define PCI_CHIP_KABYLAKE_SRV_GT1	0x590A
 #define PCI_CHIP_KABYLAKE_WKS_GT2	0x591D
 
+#define PCI_CHIP_AMBERLAKE_ULX_GT2_1	0x591C
+#define PCI_CHIP_AMBERLAKE_ULX_GT2_2	0x87C0
+
 #define PCI_CHIP_BROXTON_0		0x0A84
 #define PCI_CHIP_BROXTON_1		0x1A84
 #define PCI_CHIP_BROXTON_2		0x5A84
@@ -468,12 +470,13 @@ 
 #define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0	|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_M_GT2	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2	|| \
-				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
+				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
+				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1	|| \
+				 (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
 
 #define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0	|| \
 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1	|| \