diff mbox

drm/pl111: Use 64-bit arithmetic instead of 32-bit

Message ID 20180703235119.GA20877@embeddedor.com (mailing list archive)
State New, archived
Headers show

Commit Message

Gustavo A. R. Silva July 3, 2018, 11:51 p.m. UTC
Add suffix UL to constant 1000 in order to give the compiler complete
information about the proper arithmetic to use.

Notice that such constant is used in a context that expects an
expression of type u64 (64 bits, unsigned) and the following
expression is currently being evaluated using 32-bit arithmetic:

mode->clock * 1000

Addresses-Coverity-ID: 1466139 ("Unintentional integer overflow")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
---
 drivers/gpu/drm/pl111/pl111_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Gustavo A. R. Silva July 4, 2018, 2:11 p.m. UTC | #1
Hi,

Please, ignore this. I should have used ULL instead of UL.

I'll send v2 shortly.

Thanks
--
Gustavo

On 07/03/2018 06:51 PM, Gustavo A. R. Silva wrote:
> Add suffix UL to constant 1000 in order to give the compiler complete
> information about the proper arithmetic to use.
> 
> Notice that such constant is used in a context that expects an
> expression of type u64 (64 bits, unsigned) and the following
> expression is currently being evaluated using 32-bit arithmetic:
> 
> mode->clock * 1000
> 
> Addresses-Coverity-ID: 1466139 ("Unintentional integer overflow")
> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
> ---
>  drivers/gpu/drm/pl111/pl111_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
> index a432eb7..61d51b4 100644
> --- a/drivers/gpu/drm/pl111/pl111_display.c
> +++ b/drivers/gpu/drm/pl111/pl111_display.c
> @@ -63,7 +63,7 @@ pl111_mode_valid(struct drm_crtc *crtc,
>  	 * We use the pixelclock to also account for interlaced modes, the
>  	 * resulting bandwidth is in bytes per second.
>  	 */
> -	bw = mode->clock * 1000; /* In Hz */
> +	bw = mode->clock * 1000UL; /* In Hz */
>  	bw = bw * mode->hdisplay * mode->vdisplay * cpp;
>  	bw = div_u64(bw, mode->htotal * mode->vtotal);
>  
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index a432eb7..61d51b4 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -63,7 +63,7 @@  pl111_mode_valid(struct drm_crtc *crtc,
 	 * We use the pixelclock to also account for interlaced modes, the
 	 * resulting bandwidth is in bytes per second.
 	 */
-	bw = mode->clock * 1000; /* In Hz */
+	bw = mode->clock * 1000UL; /* In Hz */
 	bw = bw * mode->hdisplay * mode->vdisplay * cpp;
 	bw = div_u64(bw, mode->htotal * mode->vtotal);