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[1/2] clk: rockchip: rk3399: fix clk_i2sout parent selection bits

Message ID 1530883132-17678-1-git-send-email-anthony@amarulasolutions.com (mailing list archive)
State New, archived
Headers show

Commit Message

Anthony Brandon July 6, 2018, 1:18 p.m. UTC 
From: Alberto Panizzo <alberto@amarulasolutions.com>

Register, shift and mask were wrong according to datasheet.

Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
---
 drivers/clk/rockchip/clk-rk3399.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Heiko Stuebner July 7, 2018, 10:36 p.m. UTC | #1 
Am Freitag, 6. Juli 2018, 15:18:51 CEST schrieb Anthony Brandon:
> From: Alberto Panizzo <alberto@amarulasolutions.com>
> 
> Register, shift and mask were wrong according to datasheet.
> 
> Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
> Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>

applied for 4.19, after double-checking against the TRM

Thanks for catching this
Heiko
diff mbox

Patch

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index bca10d6..2a8634a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -631,7 +631,7 @@  static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
 			RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
 	COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
-			RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
+			RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
 			RK3399_CLKGATE_CON(8), 12, GFLAGS),
 
 	/* uart */