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[v2,2/2] drm/i915/skl: distribute DDB based on panel resolution

Message ID 20180731142445.30723-3-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show
Series distribute DDB based on panel resolution | expand

Commit Message

Kumar, Mahesh July 31, 2018, 2:24 p.m. UTC
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be enabled with 2 low resolution
displays.

Main contributing factor for DDB requirement is width of the display.
This patch make changes to distribute ddb based on display width.
So display with higher width will get bigger chunk of DDB.

Changes Since V1:
 - pipe_size/ddb_size will not overflow u16 so use appropriate
   data-types during computation (Chris)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107113
Cc: raviraj.p.sitaram@intel.com
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 54 +++++++++++++++++++++++++++++++----------
 1 file changed, 41 insertions(+), 13 deletions(-)

Comments

Chris Wilson July 31, 2018, 9:53 p.m. UTC | #1
Quoting Mahesh Kumar (2018-07-31 15:24:45)
> +       for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> +               const struct drm_display_mode *adjusted_mode;
> +               int hdisplay, vdisplay;
> +               enum pipe pipe;
> +
> +               if (!crtc_state->enable)
> +                       continue;
> +
> +               pipe = to_intel_crtc(crtc)->pipe;
> +               adjusted_mode = &crtc_state->adjusted_mode;
> +               drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);

You should check with Ville whether the adjusted_mode is already
adjusted. But at any rate hdisplay is not affected by hv_timing.

> +               total_width += hdisplay;
> +
> +               if (pipe < for_pipe)
> +                       width_before_pipe += hdisplay;
> +               else if (pipe == for_pipe)
> +                       pipe_width = hdisplay;
> +       }
> +
> +       ddb_size_before_pipe = (ddb_size * width_before_pipe) / total_width;

ddb_size_before_pipe can just be alloc->start.
(brackets here) are redundant, so have a discussion as to whether they
aide or hinder comprehension.

> +       pipe_size = (ddb_size * pipe_width) / total_width;
> +       alloc->start = ddb_size_before_pipe;
>         alloc->end = alloc->start + pipe_size;

To avoid truncation fun (and prev_crtc->end != this_crtc->start), use
alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 91120560a61b..3a0b5a60f73c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3814,8 +3814,13 @@  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_crtc *for_crtc = cstate->base.crtc;
+	const struct drm_crtc_state *crtc_state;
+	const struct drm_crtc *crtc;
+	u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
+	enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
 	u16 pipe_size, ddb_size;
-	int nth_active_pipe;
+	u16 ddb_size_before_pipe;
+	u32 i;
 
 	if (WARN_ON(!state) || !cstate->base.active) {
 		alloc->start = 0;
@@ -3833,14 +3838,14 @@  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 				      *num_active, ddb);
 
 	/*
-	 * If the state doesn't change the active CRTC's, then there's
-	 * no need to recalculate; the existing pipe allocation limits
-	 * should remain unchanged.  Note that we're safe from racing
-	 * commits since any racing commit that changes the active CRTC
-	 * list would need to grab _all_ crtc locks, including the one
-	 * we currently hold.
+	 * If the state doesn't change the active CRTC's or there is no
+	 * modeset request, then there's no need to recalculate;
+	 * the existing pipe allocation limits should remain unchanged.
+	 * Note that we're safe from racing commits since any racing commit
+	 * that changes the active CRTC list or do modeset would need to
+	 * grab _all_ crtc locks, including the one we currently hold.
 	 */
-	if (!intel_state->active_pipe_changes) {
+	if (!intel_state->active_pipe_changes && !intel_state->modeset) {
 		/*
 		 * alloc may be cleared by clear_intel_crtc_state,
 		 * copy from old state to be sure
@@ -3849,10 +3854,33 @@  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 		return;
 	}
 
-	nth_active_pipe = hweight32(intel_state->active_crtcs &
-				    (drm_crtc_mask(for_crtc) - 1));
-	pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
-	alloc->start = nth_active_pipe * ddb_size / *num_active;
+	/*
+	 * Watermark/ddb requirement highly depends upon width of the
+	 * framebuffer, So instead of allocating DDB equally among pipes
+	 * distribute DDB based on resolution/width of the display.
+	 */
+	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+		const struct drm_display_mode *adjusted_mode;
+		int hdisplay, vdisplay;
+		enum pipe pipe;
+
+		if (!crtc_state->enable)
+			continue;
+
+		pipe = to_intel_crtc(crtc)->pipe;
+		adjusted_mode = &crtc_state->adjusted_mode;
+		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
+		total_width += hdisplay;
+
+		if (pipe < for_pipe)
+			width_before_pipe += hdisplay;
+		else if (pipe == for_pipe)
+			pipe_width = hdisplay;
+	}
+
+	ddb_size_before_pipe = (ddb_size * width_before_pipe) / total_width;
+	pipe_size = (ddb_size * pipe_width) / total_width;
+	alloc->start = ddb_size_before_pipe;
 	alloc->end = alloc->start + pipe_size;
 }
 
@@ -5259,7 +5287,7 @@  skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 	 * any other display updates race with this transaction, so we need
 	 * to grab the lock on *all* CRTC's.
 	 */
-	if (intel_state->active_pipe_changes) {
+	if (intel_state->active_pipe_changes || intel_state->modeset) {
 		realloc_pipes = ~0;
 		intel_state->wm_results.dirty_pipes = ~0;
 	}