[1/2] ARM: dts: exynos: Convert exynos5250.dtsi to opp-v2 bindings
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Message ID 20180803065156eucas1p11664d8adddb5f481eb83fc60879ac542~HTTuAQaDG1343313433eucas1p1L@eucas1p1.samsung.com
State Superseded
Headers show
Series
  • Exynos5250: Fix suspend/resume support
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Commit Message

Marek Szyprowski Aug. 3, 2018, 6:51 a.m. UTC
Convert Exynos5250 to OPP-v2 bindings. This is a preparation to add proper
support for suspend operation point, which cannot be marked in opp-v1.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi | 130 ++++++++++++++++++++----------
 1 file changed, 88 insertions(+), 42 deletions(-)

Comments

Chanwoo Choi Aug. 3, 2018, 6:58 a.m. UTC | #1
Hi Marek,

On 2018년 08월 03일 15:51, Marek Szyprowski wrote:
> Convert Exynos5250 to OPP-v2 bindings. This is a preparation to add proper
> support for suspend operation point, which cannot be marked in opp-v1.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi | 130 ++++++++++++++++++++----------
>  1 file changed, 88 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index da163a40af15..8746189990eb 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -54,62 +54,108 @@
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0>;
> -			clock-frequency = <1700000000>;
>  			clocks = <&clock CLK_ARM_CLK>;
>  			clock-names = "cpu";
> -			clock-latency = <140000>;
> -
> -			operating-points = <
> -				1700000 1300000
> -				1600000 1250000
> -				1500000 1225000
> -				1400000 1200000
> -				1300000 1150000
> -				1200000 1125000
> -				1100000 1100000
> -				1000000 1075000
> -				 900000 1050000
> -				 800000 1025000
> -				 700000 1012500
> -				 600000 1000000
> -				 500000  975000
> -				 400000  950000
> -				 300000  937500
> -				 200000  925000
> -			>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  			#cooling-cells = <2>; /* min followed by max */
>  		};
>  		cpu@1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <1>;
> -			clock-frequency = <1700000000>;
>  			clocks = <&clock CLK_ARM_CLK>;
>  			clock-names = "cpu";
> -			clock-latency = <140000>;
> -
> -			operating-points = <
> -				1700000 1300000
> -				1600000 1250000
> -				1500000 1225000
> -				1400000 1200000
> -				1300000 1150000
> -				1200000 1125000
> -				1100000 1100000
> -				1000000 1075000
> -				 900000 1050000
> -				 800000 1025000
> -				 700000 1012500
> -				 600000 1000000
> -				 500000  975000
> -				 400000  950000
> -				 300000  937500
> -				 200000  925000
> -			>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  			#cooling-cells = <2>; /* min followed by max */
>  		};
>  	};
>  
> +	cpu0_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-200000000 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <925000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <937500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <950000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <975000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <1012500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1025000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1050000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1075000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1125000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1150000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt = <1200000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <1225000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp-1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <1300000>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
>  	soc: soc {
>  		sysram@2020000 {
>  			compatible = "mmio-sram";
> 

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Bartlomiej Zolnierkiewicz Aug. 3, 2018, 9:54 a.m. UTC | #2
On Friday, August 03, 2018 08:51:46 AM Marek Szyprowski wrote:
> Convert Exynos5250 to OPP-v2 bindings. This is a preparation to add proper
> support for suspend operation point, which cannot be marked in opp-v1.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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Patch
diff mbox series

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index da163a40af15..8746189990eb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -54,62 +54,108 @@ 
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
-			clock-frequency = <1700000000>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-names = "cpu";
-			clock-latency = <140000>;
-
-			operating-points = <
-				1700000 1300000
-				1600000 1250000
-				1500000 1225000
-				1400000 1200000
-				1300000 1150000
-				1200000 1125000
-				1100000 1100000
-				1000000 1075000
-				 900000 1050000
-				 800000 1025000
-				 700000 1012500
-				 600000 1000000
-				 500000  975000
-				 400000  950000
-				 300000  937500
-				 200000  925000
-			>;
+			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 		};
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <1>;
-			clock-frequency = <1700000000>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-names = "cpu";
-			clock-latency = <140000>;
-
-			operating-points = <
-				1700000 1300000
-				1600000 1250000
-				1500000 1225000
-				1400000 1200000
-				1300000 1150000
-				1200000 1125000
-				1100000 1100000
-				1000000 1075000
-				 900000 1050000
-				 800000 1025000
-				 700000 1012500
-				 600000 1000000
-				 500000  975000
-				 400000  950000
-				 300000  937500
-				 200000  925000
-			>;
+			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 		};
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <925000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <937500>;
+			clock-latency-ns = <140000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <975000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <1012500>;
+			clock-latency-ns = <140000>;
+		};
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1025000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1050000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1075000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1125000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1150000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1200000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1225000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1300000>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
 	soc: soc {
 		sysram@2020000 {
 			compatible = "mmio-sram";