| Message ID | 1533576828-8212-1-git-send-email-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming | expand |
On Mon, Aug 06, 2018 at 10:33:48AM -0700, Anusha Srivatsa wrote: > Add the newly added slice_row_per_frame parameter > in the Picture Parameter Set registers. > Might be helpful to specify that this indicates number of slices stacked in vertical direction when DSC is enabled. With this: Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > Credits to Manasi for noticing bSpec change. > > Suggested-by: Manasi Navare <manasi.d.navare@intel.com> > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4b656f3..f868684 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10683,6 +10683,7 @@ enum skl_power_gate { > #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ > _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) > +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) > #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) > #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) > > -- > 2.7.4 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4b656f3..f868684 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10683,6 +10683,7 @@ enum skl_power_gate { #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
Add the newly added slice_row_per_frame parameter in the Picture Parameter Set registers. Credits to Manasi for noticing bSpec change. Suggested-by: Manasi Navare <manasi.d.navare@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + 1 file changed, 1 insertion(+)