From patchwork Tue Aug 7 23:05:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10559331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BEDFD14E2 for ; Tue, 7 Aug 2018 23:10:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE51429F8C for ; Tue, 7 Aug 2018 23:10:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A27FC29F96; Tue, 7 Aug 2018 23:10:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3E5C929F8C for ; Tue, 7 Aug 2018 23:10:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73DBE6E47D; Tue, 7 Aug 2018 23:10:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22CE46E46A for ; Tue, 7 Aug 2018 23:10:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2018 16:10:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,456,1526367600"; d="scan'208";a="64335766" Received: from anusha-dev.jf.intel.com ([10.7.198.63]) by orsmga006.jf.intel.com with ESMTP; 07 Aug 2018 16:10:04 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Aug 2018 16:05:31 -0700 Message-Id: <1533683132-21625-5-git-send-email-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533683132-21625-1-git-send-email-anusha.srivatsa@intel.com> References: <1533683132-21625-1-git-send-email-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [PATCH 4/5] i915/dp/fec: Configure the Forward Error Correction bits. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: "Srivatsa, Anusha" If FEC is supported, the corresponding DP_TP_CTL register bits have to be configured. The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and wait till FEC_STATUS in DP_TP_CTL[28] is 1. Also add the warn message to make sure that the control register is already active while enabling FEC. v2: - Change commit message. Configure fec state after link training (Manasi, Gaurav) - Remove redundent checks (Manasi) - Remove the registers that get added automagically (Anusha) v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav) Cc: Gaurav K Singh Cc: Jani Nikula Cc: Ville Syrjala Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 ++- 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0ae38b6..80a10969 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9151,6 +9151,7 @@ enum skl_power_gate { #define _DP_TP_CTL_B 0x64140 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) #define DP_TP_CTL_ENABLE (1 << 31) +#define DP_TP_CTL_FEC_ENABLE (1 << 30) #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) @@ -9169,6 +9170,7 @@ enum skl_power_gate { #define _DP_TP_STATUS_A 0x64044 #define _DP_TP_STATUS_B 0x64144 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) #define DP_TP_STATUS_IDLE_DONE (1 << 25) #define DP_TP_STATUS_ACT_SENT (1 << 24) #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 9cdcc31..27fbfb7 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2829,6 +2829,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, DP_DECOMPRESSION_EN); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); intel_dp_start_link_train(intel_dp); + intel_dp_enable_fec_state(intel_dp, crtc_state); + if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5ef9005..1651da4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2965,6 +2965,33 @@ void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n"); } +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + enum port port = intel_dig_port->base.port; + u32 val; + + /* FEC support exists for DP 1.4 only */ + if (intel_dp_is_edp(intel_dp)) + return; + + /* If Display Compression is not enabled, FEC need not be configured */ + if (!crtc_state->dsc_params.compression_enable) + return; + + val = I915_READ(DP_TP_CTL(port)); + val |= DP_TP_CTL_FEC_ENABLE; + I915_WRITE(DP_TP_CTL(port), val); + + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port), + DP_TP_STATUS_FEC_ENABLE_LIVE, + DP_TP_STATUS_FEC_ENABLE_LIVE, + 1)) + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); +} + /* If the sink supports it, try to set the power state appropriately */ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1ab9b20..117ddaf 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1519,7 +1519,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder); bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port); - enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -1699,6 +1698,8 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int state); +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder);