From patchwork Thu Aug 23 15:12:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacopo Mondi X-Patchwork-Id: 10574249 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA3BD13B6 for ; Thu, 23 Aug 2018 15:12:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98E512C104 for ; Thu, 23 Aug 2018 15:12:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C67C2C285; Thu, 23 Aug 2018 15:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FF992C104 for ; Thu, 23 Aug 2018 15:12:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732488AbeHWSmf (ORCPT ); Thu, 23 Aug 2018 14:42:35 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:53661 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732016AbeHWSmf (ORCPT ); Thu, 23 Aug 2018 14:42:35 -0400 X-Originating-IP: 2.224.242.101 Received: from w540.lan (2-224-242-101.ip172.fastwebnet.it [2.224.242.101]) (Authenticated sender: jacopo@jmondi.org) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 3922DE000F; Thu, 23 Aug 2018 15:12:28 +0000 (UTC) From: Jacopo Mondi To: Laurent Pinchart , David Airlie Cc: Jacopo Mondi , ulrich.hecht+renesas@gmail.com, kieran.bingham@ideasonboard.com, dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR RENESAS), linux-renesas-soc@vger.kernel.org (open list:DRM DRIVERS FOR RENESAS) Subject: [PATCH 1/4] drm: rcar-du: Do not write ESCR for DPLL channels Date: Thu, 23 Aug 2018 17:12:11 +0200 Message-Id: <1535037134-373-2-git-send-email-jacopo+renesas@jmondi.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to revision 1.00 of R-Car Gen3 Soc manual, writing to ESCR register of DU channels equipped with a display PLL (DPLL) is invalid. Fix this by writing ESCR only for channels making use of the DU internal post-divider to generate the dotclockout signal, with R-Car H3 ES1.x being a notable exception. Signed-off-by: Jacopo Mondi --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 1541152..7b1c05b 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -246,7 +246,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) struct rcar_du_device *rcdu = rcrtc->group->dev; unsigned long mode_clock = mode->clock * 1000; u32 dsmr; - u32 escr; if (rcdu->info->dpll_mask & (1 << rcrtc->index)) { unsigned long target = mode_clock; @@ -293,7 +292,11 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); - escr = ESCR_DCLKSEL_DCLKIN | div; + /* Only H3 ES1.x has a post divider when a DPLL is present. */ + if (soc_device_match(rcar_du_r8a7795_es1)) + rcar_du_crtc_write(rcrtc, + rcrtc->index % 2 ? ESCR13 : ESCR02, + ESCR_DCLKSEL_DCLKIN | div); } else { struct du_clk_params params = { .diff = (unsigned long)-1 }; @@ -308,12 +311,10 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) params.rate); clk_set_rate(params.clk, params.rate); - escr = params.escr; + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, + params.escr); } - dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); - - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); /* Signal polarities */