[kvm-unit-tests,v2,4/5] s390x: save/restore cr0 in IRQ handlers
diff mbox series

Message ID 20180829154750.12876-5-david@redhat.com
State New
Headers show
Series
  • s390x: simple DXC test
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Commit Message

David Hildenbrand Aug. 29, 2018, 3:47 p.m. UTC
We want to check for certain conditions (e.g. no AFP enabled), but still
have it correctly set up (AFP enabled) in the IRQ handlers. So let's
save + restore.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 lib/s390x/asm-offsets.c  | 1 +
 lib/s390x/asm/arch_def.h | 4 +++-
 s390x/cstart64.S         | 7 +++++++
 3 files changed, 11 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c
index f1012c6..6e2d259 100644
--- a/lib/s390x/asm-offsets.c
+++ b/lib/s390x/asm-offsets.c
@@ -57,6 +57,7 @@  int main(void)
 	OFFSET(GEN_LC_SW_INT_GRS, lowcore, sw_int_grs);
 	OFFSET(GEN_LC_SW_INT_FPRS, lowcore, sw_int_fprs);
 	OFFSET(GEN_LC_SW_INT_FPC, lowcore, sw_int_fpc);
+	OFFSET(GEN_LC_SW_INT_CR0, lowcore, sw_int_cr0);
 	OFFSET(GEN_LC_MCCK_EXT_SA_ADDR, lowcore, mcck_ext_sa_addr);
 	OFFSET(GEN_LC_FPRS_SA, lowcore, fprs_sa);
 	OFFSET(GEN_LC_GRS_SA, lowcore, grs_sa);
diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index 99abe18..d2cd727 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -71,7 +71,9 @@  struct lowcore {
 	uint64_t	sw_int_grs[16];			/* 0x0200 */
 	uint64_t	sw_int_fprs[16];		/* 0x0280 */
 	uint32_t	sw_int_fpc;			/* 0x0300 */
-	uint8_t		pad_0x0304[0x11b0 - 0x0304];	/* 0x0304 */
+	uint8_t		pad_0x0304[0x0308 - 0x0304];	/* 0x0304 */
+	uint64_t	sw_int_cr0;			/* 0x0308 */
+	uint8_t		pad_0x0310[0x11b0 - 0x0310];	/* 0x0310 */
 	uint64_t	mcck_ext_sa_addr;		/* 0x11b0 */
 	uint8_t		pad_0x11b8[0x1200 - 0x11b8];	/* 0x11b8 */
 	uint64_t	fprs_sa[16];			/* 0x1200 */
diff --git a/s390x/cstart64.S b/s390x/cstart64.S
index c38ebc0..d6d40b7 100644
--- a/s390x/cstart64.S
+++ b/s390x/cstart64.S
@@ -57,6 +57,11 @@  init_psw_cont:
 	.macro SAVE_REGS
 	/* save grs 0-15 */
 	stmg	%r0, %r15, GEN_LC_SW_INT_GRS
+	/* save cr0 */
+	stctg	%c0, %c0, GEN_LC_SW_INT_CR0
+	/* load initial cr0 again */
+	larl	%r1, initial_cr0
+	lctlg	%c0, %c0, 0(%r1)
 	/* save fprs 0-15 + fpc */
 	la	%r1, GEN_LC_SW_INT_FPRS
 	std	%f0, 0(%r1)
@@ -98,6 +103,8 @@  init_psw_cont:
 	ld	%f14, 112(%r1)
 	ld	%f15, 120(%r1)
 	lfpc	GEN_LC_SW_INT_FPC
+	/* restore cr0 */
+	lctlg	%c0, %c0, GEN_LC_SW_INT_CR0
 	/* restore grs 0-15 */
 	lmg	%r0, %r15, GEN_LC_SW_INT_GRS
 	.endm