From patchwork Sat Sep 8 20:54:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10593187 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EF1D14E2 for ; Sat, 8 Sep 2018 20:54:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7025D2932B for ; Sat, 8 Sep 2018 20:54:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6378929332; Sat, 8 Sep 2018 20:54:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4DC92932B for ; Sat, 8 Sep 2018 20:54:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726638AbeIIBlN (ORCPT ); Sat, 8 Sep 2018 21:41:13 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:43970 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726444AbeIIBlN (ORCPT ); Sat, 8 Sep 2018 21:41:13 -0400 Received: by mail-lf1-f67.google.com with SMTP id h64-v6so14597132lfi.10 for ; Sat, 08 Sep 2018 13:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:organization:message-id:date:user-agent :mime-version:content-language:content-transfer-encoding; bh=xanbOOdvewa6RtAoD78oL1LRQjzFVhJugxHg5q0EvpY=; b=ZvRJnpxbtglDoHVegIdyqqLr4MCZrqC1bSzELAu/igJX+dHVGyIRgb1OMLhZxERVwX NdtO7/rSBlbjM5viGf8pUG0DfzISoEFXICjtf2K/y43d2JBilNzLkRXP7yxIgeAIXXaf JbfrVOPPxE4P8+3z6VZT6uhXX8YOV9eQkD63jSKCQH4NMyp68neTTeay4raUwZXFY8Ff TenB3rTGElH5VbDbMHUoYKtJ1kzs70xnBfvDLhctYKh+Ar2G6QrZlyuXRNQ55Me8R1Mc eF5tMwgSlpnvz/IqLthHUaLy18ZCCdJC9eaJ9UfzgrhPN3zrtY2xVrq8MdIooE6wWzRu MG7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:organization:message-id:date :user-agent:mime-version:content-language:content-transfer-encoding; bh=xanbOOdvewa6RtAoD78oL1LRQjzFVhJugxHg5q0EvpY=; b=antAeBb2wnnIZkqHxoOj907B0i65RBavUoZgJhnP1o+agAHPzc+ub793yW0QThfrR3 q9cjPZoNRocgVFdfOTE3CR4kYJ/wuMTw0uPrAnL5sXPjah2TTgNlhIWvIOVEg7ror5gA fxXBFKhn2etvcI7mhwYMgB1PKxq4Ao//xRoaWBVLv6bDw5oQI6i+U9LbLV3N+AyQQUNi 8oHQlQXA8aU7QB0dTVAd46rglYcWTNwP6gJd7/NpwD4QtD2xxmRGCyVYRMaI2Baf/CF9 sD/FlWuzVyf3KHSNjvPcvLHTqrzCqQcaq0+gZ87DG9szMKNwftT7OXbS64Fy2yRjas4t 8htg== X-Gm-Message-State: APzg51CwntDXAL5YoJH8RZKKWFAb/EhR+CVcG3eFBkJOF3FAv6599on8 8S4r7YB7+Xc7xvveVOGVPBmxhA== X-Google-Smtp-Source: ANB0VdZCpkZvbLpkX+pCndnCjoxFkYLgLuCkXbxV5tQF9Ee7Fk4m2btuycarjD4YuTnLxY1/QnK2/w== X-Received: by 2002:a19:8d45:: with SMTP id p66-v6mr8245651lfd.44.1536440048216; Sat, 08 Sep 2018 13:54:08 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.82.154]) by smtp.gmail.com with ESMTPSA id u24-v6sm1893819lji.4.2018.09.08.13.54.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Sep 2018 13:54:06 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH v3] clocksource: sh_cmt: fixup for 64-bit machines To: Daniel Lezcano , Thomas Gleixner , linux-renesas-soc@vger.kernel.org Cc: Vladimir Barinov , Andrey Gusakov , Mikhail Ulyanov , linux-sh@vger.kernel.org Organization: Cogent Embedded Message-ID: <46a8a01b-e849-6d62-3c61-fbae48f34e58@cogentembedded.com> Date: Sat, 8 Sep 2018 23:54:05 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 Content-Language: en-MW Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed that 'max_delta_ns' for the broadcast timer (CMT) was shown as 1000 in /proc/timer_list. It turned out that when calculating it, the driver did 1 << 32 (causing what I think was undefined behavior) resulting in a zero delta, later clamped to 1000 by cev_delta2ns(). The root cause turned out to be that the driver abused *unsigned long* for the CMT register values (which are 16/32-bit), so that the calculation of 'ch->max_match_value' in sh_cmt_setup_channel() used the wrong branch. Using more proper 'u32' instead fixed 'max_delta_ns' and even fixed the switching an active clocksource to CMT (which caused the system to turn non-interactive before). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- This patch is against the 'tip.git' repo's 'timers/core' branch. The CMT driver wasn't ever used on SH64; on R-Car gen3 (ARM64) I'm only enabling building of this driver now, so not sure how urgent is this... Changes in version 3: - made the 'overflow_bit' and 'clear_bits' members of 'struct sh_cmt_info' 'u32'; - made the 2nd parameter of sh_cmt_write_cmstr() 'u32'; - made the result, the 2nd parameter, and 'o{1|2}' local variables of sh_cmt_get_counter() 'u32'; - made the 'has_wrapped' local variables 'u32' in sh_cmt_clocksource_read() and sh_cmt_clock_event_program_verify(); - fixed a typo in the patch description. Changes in version 2: - completely redid the patch, fixing abuse of *unsigned long* for the CMT register values. drivers/clocksource/sh_cmt.c | 72 +++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 39 deletions(-) Index: tip/drivers/clocksource/sh_cmt.c =================================================================== --- tip.orig/drivers/clocksource/sh_cmt.c +++ tip/drivers/clocksource/sh_cmt.c @@ -78,18 +78,17 @@ struct sh_cmt_info { unsigned int channels_mask; unsigned long width; /* 16 or 32 bit version of hardware block */ - unsigned long overflow_bit; - unsigned long clear_bits; + u32 overflow_bit; + u32 clear_bits; /* callbacks for CMSTR and CMCSR access */ - unsigned long (*read_control)(void __iomem *base, unsigned long offs); + u32 (*read_control)(void __iomem *base, unsigned long offs); void (*write_control)(void __iomem *base, unsigned long offs, - unsigned long value); + u32 value); /* callbacks for CMCNT and CMCOR access */ - unsigned long (*read_count)(void __iomem *base, unsigned long offs); - void (*write_count)(void __iomem *base, unsigned long offs, - unsigned long value); + u32 (*read_count)(void __iomem *base, unsigned long offs); + void (*write_count)(void __iomem *base, unsigned long offs, u32 value); }; struct sh_cmt_channel { @@ -103,9 +102,9 @@ struct sh_cmt_channel { unsigned int timer_bit; unsigned long flags; - unsigned long match_value; - unsigned long next_match_value; - unsigned long max_match_value; + u32 match_value; + u32 next_match_value; + u32 max_match_value; raw_spinlock_t lock; struct clock_event_device ced; struct clocksource cs; @@ -160,24 +159,22 @@ struct sh_cmt_device { #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) -static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) +static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) { return ioread16(base + (offs << 1)); } -static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) +static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) { return ioread32(base + (offs << 2)); } -static void sh_cmt_write16(void __iomem *base, unsigned long offs, - unsigned long value) +static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) { iowrite16(value, base + (offs << 1)); } -static void sh_cmt_write32(void __iomem *base, unsigned long offs, - unsigned long value) +static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) { iowrite32(value, base + (offs << 2)); } @@ -242,7 +239,7 @@ static const struct sh_cmt_info sh_cmt_i #define CMCNT 1 /* channel register */ #define CMCOR 2 /* channel register */ -static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) { if (ch->iostart) return ch->cmt->info->read_control(ch->iostart, 0); @@ -250,8 +247,7 @@ static inline unsigned long sh_cmt_read_ return ch->cmt->info->read_control(ch->cmt->mapbase, 0); } -static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, - unsigned long value) +static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) { if (ch->iostart) ch->cmt->info->write_control(ch->iostart, 0, value); @@ -259,39 +255,35 @@ static inline void sh_cmt_write_cmstr(st ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); } -static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) { return ch->cmt->info->read_control(ch->ioctrl, CMCSR); } -static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, - unsigned long value) +static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) { ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); } -static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) { return ch->cmt->info->read_count(ch->ioctrl, CMCNT); } -static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, - unsigned long value) +static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) { ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); } -static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, - unsigned long value) +static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) { ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); } -static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, - int *has_wrapped) +static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) { - unsigned long v1, v2, v3; - int o1, o2; + u32 v1, v2, v3; + u32 o1, o2; o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; @@ -311,7 +303,8 @@ static unsigned long sh_cmt_get_counter( static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) { - unsigned long flags, value; + unsigned long flags; + u32 value; /* start stop register shared by multiple timer channels */ raw_spin_lock_irqsave(&ch->cmt->lock, flags); @@ -418,11 +411,11 @@ static void sh_cmt_disable(struct sh_cmt static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, int absolute) { - unsigned long new_match; - unsigned long value = ch->next_match_value; - unsigned long delay = 0; - unsigned long now = 0; - int has_wrapped; + u32 value = ch->next_match_value; + u32 new_match; + u32 delay = 0; + u32 now = 0; + u32 has_wrapped; now = sh_cmt_get_counter(ch, &has_wrapped); ch->flags |= FLAG_REPROGRAM; /* force reprogram */ @@ -619,9 +612,10 @@ static struct sh_cmt_channel *cs_to_sh_c static u64 sh_cmt_clocksource_read(struct clocksource *cs) { struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); - unsigned long flags, raw; + unsigned long flags; unsigned long value; - int has_wrapped; + u32 has_wrapped; + u32 raw; raw_spin_lock_irqsave(&ch->lock, flags); value = ch->total_cycles;