drm/i915: Make 48bit full ppgtt configuration generic (v3)
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Message ID 20180910171225.30872-1-bob.j.paauwe@intel.com
State New
Headers show
Series
  • drm/i915: Make 48bit full ppgtt configuration generic (v3)
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Commit Message

Bob Paauwe Sept. 10, 2018, 5:12 p.m. UTC
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.

v2: keep USES_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>

Additional work to rename 48bit to 4 level

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
 drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
 drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 13 files changed, 39 insertions(+), 32 deletions(-)

Comments

Rodrigo Vivi Sept. 10, 2018, 5:32 p.m. UTC | #1
On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> 
> v2: keep USES_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
>     Remove unecessary line coninuations (Bob)
>     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> 
> Additional work to rename 48bit to 4 level

Thanks for the additional work.
Bikeshed on this comment here: Shouldn't this be mentioned on the
"v3" portion directly instead of the middle of tags' block?

> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
>  drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
>  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
>  drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
>  drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
>  drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
>  drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  13 files changed, 39 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index a4e8e3cf74fd..52bebd67173a 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
>  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>  
> -	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> +	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a4da5b723fd..a367686fd735 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)

another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>  	GEM_BUG_ON((sizes) == 0); \
>  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f15a039772db..1add339ca6be 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
>  	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>  
>  	address_mode = INTEL_LEGACY_32B_CONTEXT;
> -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
>  		address_mode = INTEL_LEGACY_64B_CONTEXT;
>  	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index eb0e446d6482..c66bbf409791 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  			       	int enable_ppgtt)
>  {
>  	bool has_full_ppgtt;
> -	bool has_full_48bit_ppgtt;
> +	bool has_full_4lvl_ppgtt;
>  
>  	if (!dev_priv->info.has_aliasing_ppgtt)
>  		return 0;
>  
>  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
>  
>  	if (intel_vgpu_active(dev_priv)) {
>  		/* GVT-g has no support for 32bit ppgtt */
>  		has_full_ppgtt = false;
> -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> +		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
>  	}
>  
>  	/*
> @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  	if (enable_ppgtt == 2 && has_full_ppgtt)
>  		return 2;
>  
> -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	/* Disable ppgtt on SNB if VT-d is on. */
> @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> -	if (has_full_48bit_ppgtt)
> +	if (has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	if (has_full_ppgtt)
> @@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
>  	 * page-table operating in 64K mode must point to a properly aligned 64K
>  	 * region, including any PTEs which happen to point to scratch.
>  	 *
> -	 * This is only relevant for the 48b PPGTT where we support
> +	 * This is only relevant for the 4-level PPGTT where we support
>  	 * huge-gtt-pages, see also i915_vma_insert().
>  	 *
>  	 * TODO: we should really consider write-protecting the scratch-page and
>  	 * sharing between ppgtt
>  	 */
>  	size = I915_GTT_PAGE_SIZE_4K;
> -	if (i915_vm_is_48bit(vm) &&
> +	if (i915_vm_is_4lvl(vm) &&
>  	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
>  		size = I915_GTT_PAGE_SIZE_64K;
>  		gfp |= __GFP_NOWARN;
> @@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
>  
>  static inline bool use_4lvl(const struct i915_address_space *vm)
>  {
> -	return i915_vm_is_48bit(vm);
> +	return i915_vm_is_4lvl(vm);
>  }
>  
>  static struct i915_page_directory_pointer *
> @@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>  	ppgtt->vm.i915 = i915;
>  	ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> -		1ULL << 48 :
> -		1ULL << 32;
> +	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> +	if (i915_modparams.enable_ppgtt < 3)
> +		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);

but actually this is the only real thing that holds me from putting the rv-b
right now...
I think this change deserves a separated patch, but maybe it is because
I simply didn't understand why start using this min SZ_4G and I miss
some explanation...

The rest of the patch lgtm ;)

Thanks a lot,
Rodrigo.

>  
>  	/*
>  	 * From bdw, there is support for read-only pages in the PPGTT.
> @@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
>  	enum intel_engine_id id;
>  
>  	for_each_engine(engine, dev_priv, id) {
> -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
>  				 GEN8_GFX_PPGTT_48B : 0;
>  		I915_WRITE(RING_MODE_GEN7(engine),
>  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 7e2af5f4f39b..b2a709a27cb9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -363,7 +363,7 @@ struct i915_address_space {
>  #define i915_is_ggtt(vm) ((vm)->is_ggtt)
>  
>  static inline bool
> -i915_vm_is_48bit(const struct i915_address_space *vm)
> +i915_vm_is_4lvl(const struct i915_address_space *vm)
>  {
>  	return (vm->total - 1) >> 32;
>  }
> @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
>  static inline unsigned int
>  i915_pdpes_per_pdp(const struct i915_address_space *vm)
>  {
> -	if (i915_vm_is_48bit(vm))
> +	if (i915_vm_is_4lvl(vm))
>  		return GEN8_PML4ES_PER_PML4;
>  
>  	return GEN8_3LVL_PDPES;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>  	.has_rc6p = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> +	.full_ppgtt_bits = 32, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	GEN_DEFAULT_PAGE_SIZES, \
>  	IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_hotplug = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32,
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
>  		      I915_GTT_PAGE_SIZE_2M, \
>  	.has_logical_ring_contexts = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_64bit_reloc = 1, \
>  	.has_reset_engine = 1
>  
> @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_gmch_display = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32,
>  	.has_reset_engine = 1,
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
> @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.has_guc = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_reset_engine = 1, \
>  	.has_snoop = true, \
>  	.has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..6d2f9f06ab57 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
>  /*
>   * VGT capabilities type
>   */
> -#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
> +#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
>  #define VGT_CAPS_HWSP_EMULATION		BIT(3)
>  #define VGT_CAPS_HUGE_GTT		BIT(4)
>  
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..180f2dca1223 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
>  }
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
>  {
> -	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> +	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
>  }
>  
>  struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..b830a7b5064f 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>  
>  void i915_check_vgpu(struct drm_i915_private *dev_priv);
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
>  
>  static inline bool
>  intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6eecd64734d5..50acb0463e9a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -88,7 +88,6 @@ enum intel_platform {
>  	func(has_fbc); \
>  	func(has_fpga_dbg); \
>  	func(has_full_ppgtt); \
> -	func(has_full_48bit_ppgtt); \
>  	func(has_gmch_display); \
>  	func(has_guc); \
>  	func(has_guc_ct); \
> @@ -182,6 +181,9 @@ struct intel_device_info {
>  		u16 degamma_lut_size;
>  		u16 gamma_lut_size;
>  	} color;
> +
> +	/* PPGTT bit size */
> +	int full_ppgtt_bits;
>  };
>  
>  struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index def467c2451b..52a86a8c06b7 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
>  	 * PML4 is allocated during ppgtt init, so this is not needed
>  	 * in 48-bit mode.
>  	 */
> -	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
> +	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
>  		execlists_update_context_pdps(ppgtt, reg_state);
>  
>  	return ce->lrc_desc;
> @@ -2019,7 +2019,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>  	 * not needed in 48-bit.*/
>  	if (rq->gem_context->ppgtt &&
>  	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> -	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> +	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
>  	    !intel_vgpu_active(rq->i915)) {
>  		ret = intel_logical_ring_emit_pdps(rq);
>  		if (ret)
> @@ -2688,8 +2688,8 @@ static void execlists_init_reg_state(u32 *regs,
>  	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
>  	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>  
> -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
> -		/* 64b PPGTT (48bit canonical)
> +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
> +		/* > 32b PPGTT
>  		 * PDP0_DESCRIPTOR contains the base address to PML4 and
>  		 * other PDP Descriptors are ignored.
>  		 */
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index e272127783fe..b065630bf672 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
>  	 * huge-gtt-pages.
>  	 */
>  
> -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> -		pr_info("48b PPGTT not supported, skipping\n");
> +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
> +		pr_info("Extended range PPGTT not supported, skipping\n");
>  		return 0;
>  	}
>  
> @@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
>  		goto out_unlock;
>  	}
>  
> -	if (!i915_vm_is_48bit(&ppgtt->vm)) {
> -		pr_err("failed to create 48b PPGTT\n");
> +	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
> +		pr_err("failed to create extended PPGTT\n");
>  		err = -EINVAL;
>  		goto out_close;
>  	}
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 43ed8b28aeaa..33d7225edbbb 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
>  		I915_GTT_PAGE_SIZE_64K |
>  		I915_GTT_PAGE_SIZE_2M;
>  
> +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> +
>  	mock_uncore_init(i915);
>  	i915_gem_init__mm(i915);
>  
> -- 
> 2.14.4
>
Bob Paauwe Sept. 10, 2018, 6:51 p.m. UTC | #2
On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:

> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> > 
> > Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> > describe that a 4 level walk table extended range PPGTT is being
> > used. Add a new device info field that specifies the number of
> > bits to prepare for cases where the range is not 32 or 48 bits.
> > 
> > v2: keep USES_FULL_PPGTT() unchanged (Chris)
> > v3: Simplify condition in gen8_ppgtt_create() (Chris)
> >     Remove unecessary line coninuations (Bob)
> >     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Michel Thierry <michel.thierry@intel.com>
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > 
> > Additional work to rename 48bit to 4 level  
> 
> Thanks for the additional work.
> Bikeshed on this comment here: Shouldn't this be mentioned on the
> "v3" portion directly instead of the middle of tags' block?

Oops, that was just a rebase squash failure on my part and shouldn't be
there at all. 

> 
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
> >  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
> >  drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
> >  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
> >  drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
> >  drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
> >  drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
> >  drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
> >  drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
> >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  13 files changed, 39 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> > index a4e8e3cf74fd..52bebd67173a 100644
> > --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> > @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> >  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
> >  
> > -	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> > +	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5a4da5b723fd..a367686fd735 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
> >  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)  
> 
> another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

I don't have any strong opinion here but can see that "FULL" is a bit
redundant when thinking of this an option/enhancement to FULL_PPGTT.

> 
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >  	GEM_BUG_ON((sizes) == 0); \
> >  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..1add339ca6be 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
> >  	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> >  
> >  	address_mode = INTEL_LEGACY_32B_CONTEXT;
> > -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> > +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> >  		address_mode = INTEL_LEGACY_64B_CONTEXT;
> >  	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index eb0e446d6482..c66bbf409791 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  			       	int enable_ppgtt)
> >  {
> >  	bool has_full_ppgtt;
> > -	bool has_full_48bit_ppgtt;
> > +	bool has_full_4lvl_ppgtt;
> >  
> >  	if (!dev_priv->info.has_aliasing_ppgtt)
> >  		return 0;
> >  
> >  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
> >  
> >  	if (intel_vgpu_active(dev_priv)) {
> >  		/* GVT-g has no support for 32bit ppgtt */
> >  		has_full_ppgtt = false;
> > -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > +		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
> >  	}
> >  
> >  	/*
> > @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  	if (enable_ppgtt == 2 && has_full_ppgtt)
> >  		return 2;
> >  
> > -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	/* Disable ppgtt on SNB if VT-d is on. */
> > @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  		return 0;
> >  	}
> >  
> > -	if (has_full_48bit_ppgtt)
> > +	if (has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	if (has_full_ppgtt)
> > @@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> >  	 * page-table operating in 64K mode must point to a properly aligned 64K
> >  	 * region, including any PTEs which happen to point to scratch.
> >  	 *
> > -	 * This is only relevant for the 48b PPGTT where we support
> > +	 * This is only relevant for the 4-level PPGTT where we support
> >  	 * huge-gtt-pages, see also i915_vma_insert().
> >  	 *
> >  	 * TODO: we should really consider write-protecting the scratch-page and
> >  	 * sharing between ppgtt
> >  	 */
> >  	size = I915_GTT_PAGE_SIZE_4K;
> > -	if (i915_vm_is_48bit(vm) &&
> > +	if (i915_vm_is_4lvl(vm) &&
> >  	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
> >  		size = I915_GTT_PAGE_SIZE_64K;
> >  		gfp |= __GFP_NOWARN;
> > @@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
> >  
> >  static inline bool use_4lvl(const struct i915_address_space *vm)
> >  {
> > -	return i915_vm_is_48bit(vm);
> > +	return i915_vm_is_4lvl(vm);
> >  }
> >  
> >  static struct i915_page_directory_pointer *
> > @@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> >  	ppgtt->vm.i915 = i915;
> >  	ppgtt->vm.dma = &i915->drm.pdev->dev;
> >  
> > -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > -		1ULL << 48 :
> > -		1ULL << 32;
> > +	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> > +	if (i915_modparams.enable_ppgtt < 3)
> > +		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);  
> 
> but actually this is the only real thing that holds me from putting the rv-b
> right now...
> I think this change deserves a separated patch, but maybe it is because
> I simply didn't understand why start using this min SZ_4G and I miss
> some explanation...

This was based on Chris's suggestion. But if it makes more sense to
force it to 32 bit now with:

if (i915_modeparams.enable_ppgtt < 3)
	ppgtt->vm.total = 1ULL << 32

I can make that change.

> 
> The rest of the patch lgtm ;)
> 
> Thanks a lot,
> Rodrigo.
> 
> >  
> >  	/*
> >  	 * From bdw, there is support for read-only pages in the PPGTT.
> > @@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> >  	enum intel_engine_id id;
> >  
> >  	for_each_engine(engine, dev_priv, id) {
> > -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
> >  				 GEN8_GFX_PPGTT_48B : 0;
> >  		I915_WRITE(RING_MODE_GEN7(engine),
> >  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > index 7e2af5f4f39b..b2a709a27cb9 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > @@ -363,7 +363,7 @@ struct i915_address_space {
> >  #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> >  
> >  static inline bool
> > -i915_vm_is_48bit(const struct i915_address_space *vm)
> > +i915_vm_is_4lvl(const struct i915_address_space *vm)
> >  {
> >  	return (vm->total - 1) >> 32;
> >  }
> > @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
> >  static inline unsigned int
> >  i915_pdpes_per_pdp(const struct i915_address_space *vm)
> >  {
> > -	if (i915_vm_is_48bit(vm))
> > +	if (i915_vm_is_4lvl(vm))
> >  		return GEN8_PML4ES_PER_PML4;
> >  
> >  	return GEN8_3LVL_PDPES;
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> >  	.has_rc6p = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > +	.full_ppgtt_bits = 32, \
> >  	GEN_DEFAULT_PIPEOFFSETS, \
> >  	GEN_DEFAULT_PAGE_SIZES, \
> >  	IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> >  	.has_hotplug = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32,
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> >  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> > @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> >  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
> >  		      I915_GTT_PAGE_SIZE_2M, \
> >  	.has_logical_ring_contexts = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_64bit_reloc = 1, \
> >  	.has_reset_engine = 1
> >  
> > @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
> >  	.has_gmch_display = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32,
> >  	.has_reset_engine = 1,
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> > @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> >  	.has_guc = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_reset_engine = 1, \
> >  	.has_snoop = true, \
> >  	.has_coherent_ggtt = false, \
> > diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> > index eeaa3d506d95..6d2f9f06ab57 100644
> > --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> > +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> > @@ -52,7 +52,7 @@ enum vgt_g2v_type {
> >  /*
> >   * VGT capabilities type
> >   */
> > -#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
> > +#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
> >  #define VGT_CAPS_HWSP_EMULATION		BIT(3)
> >  #define VGT_CAPS_HUGE_GTT		BIT(4)
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> > index 869cf4a3b6de..180f2dca1223 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.c
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> > @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> >  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> >  }
> >  
> > -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> > +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
> >  {
> > -	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> > +	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
> >  }
> >  
> >  struct _balloon_info_ {
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> > index 551acc390046..b830a7b5064f 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.h
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> > @@ -28,7 +28,7 @@
> >  
> >  void i915_check_vgpu(struct drm_i915_private *dev_priv);
> >  
> > -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> > +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
> >  
> >  static inline bool
> >  intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 6eecd64734d5..50acb0463e9a 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -88,7 +88,6 @@ enum intel_platform {
> >  	func(has_fbc); \
> >  	func(has_fpga_dbg); \
> >  	func(has_full_ppgtt); \
> > -	func(has_full_48bit_ppgtt); \
> >  	func(has_gmch_display); \
> >  	func(has_guc); \
> >  	func(has_guc_ct); \
> > @@ -182,6 +181,9 @@ struct intel_device_info {
> >  		u16 degamma_lut_size;
> >  		u16 gamma_lut_size;
> >  	} color;
> > +
> > +	/* PPGTT bit size */
> > +	int full_ppgtt_bits;
> >  };
> >  
> >  struct intel_driver_caps {
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index def467c2451b..52a86a8c06b7 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
> >  	 * PML4 is allocated during ppgtt init, so this is not needed
> >  	 * in 48-bit mode.
> >  	 */
> > -	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
> > +	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
> >  		execlists_update_context_pdps(ppgtt, reg_state);
> >  
> >  	return ce->lrc_desc;
> > @@ -2019,7 +2019,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
> >  	 * not needed in 48-bit.*/
> >  	if (rq->gem_context->ppgtt &&
> >  	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> > -	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> > +	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
> >  	    !intel_vgpu_active(rq->i915)) {
> >  		ret = intel_logical_ring_emit_pdps(rq);
> >  		if (ret)
> > @@ -2688,8 +2688,8 @@ static void execlists_init_reg_state(u32 *regs,
> >  	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
> >  	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
> >  
> > -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
> > -		/* 64b PPGTT (48bit canonical)
> > +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
> > +		/* > 32b PPGTT
> >  		 * PDP0_DESCRIPTOR contains the base address to PML4 and
> >  		 * other PDP Descriptors are ignored.
> >  		 */
> > diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > index e272127783fe..b065630bf672 100644
> > --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > @@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
> >  	 * huge-gtt-pages.
> >  	 */
> >  
> > -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > -		pr_info("48b PPGTT not supported, skipping\n");
> > +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
> > +		pr_info("Extended range PPGTT not supported, skipping\n");
> >  		return 0;
> >  	}
> >  
> > @@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
> >  		goto out_unlock;
> >  	}
> >  
> > -	if (!i915_vm_is_48bit(&ppgtt->vm)) {
> > -		pr_err("failed to create 48b PPGTT\n");
> > +	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
> > +		pr_err("failed to create extended PPGTT\n");
> >  		err = -EINVAL;
> >  		goto out_close;
> >  	}
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> >  		I915_GTT_PAGE_SIZE_64K |
> >  		I915_GTT_PAGE_SIZE_2M;
> >  
> > +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> > +
> >  	mock_uncore_init(i915);
> >  	i915_gem_init__mm(i915);
> >  
> > -- 
> > 2.14.4
> >
Chris Wilson Sept. 10, 2018, 7:56 p.m. UTC | #3
Quoting Bob Paauwe (2018-09-10 18:12:25)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>         .has_rc6p = 1, \
>         .has_aliasing_ppgtt = 1, \
>         .has_full_ppgtt = 1, \
> +       .full_ppgtt_bits = 32, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
>         .has_hotplug = 1,
>         .has_aliasing_ppgtt = 1,
>         .has_full_ppgtt = 1,
> +       .full_ppgtt_bits = 32,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,

To be pedant, .bits = 31 for gen6/7.
-Chris
Bob Paauwe Sept. 10, 2018, 8:34 p.m. UTC | #4
On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> >         .has_rc6p = 1, \
> >         .has_aliasing_ppgtt = 1, \
> >         .has_full_ppgtt = 1, \
> > +       .full_ppgtt_bits = 32, \
> >         GEN_DEFAULT_PIPEOFFSETS, \
> >         GEN_DEFAULT_PAGE_SIZES, \
> >         IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> >         .has_hotplug = 1,
> >         .has_aliasing_ppgtt = 1,
> >         .has_full_ppgtt = 1,
> > +       .full_ppgtt_bits = 32,
> >         .has_snoop = true,
> >         .has_coherent_ggtt = false,
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> 
> To be pedant, .bits = 31 for gen6/7.
> -Chris

If I'm reading the code right, these use a different method of setting
the vm.total so won't use the .full_ppgtt_bits.

I don't know enough about this, but would it make sense to modify
gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
31) or maybe just not set .full_ppgtt_bits for those platforms or set
the value correctly and ignore it for now?

Bob
Chris Wilson Sept. 10, 2018, 8:35 p.m. UTC | #5
Quoting Bob Paauwe (2018-09-10 21:34:00)
> On Mon, 10 Sep 2018 20:56:51 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
> 
> > Quoting Bob Paauwe (2018-09-10 18:12:25)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index d6f7b9fe1d26..e0619952ff52 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> > >         .has_rc6p = 1, \
> > >         .has_aliasing_ppgtt = 1, \
> > >         .has_full_ppgtt = 1, \
> > > +       .full_ppgtt_bits = 32, \
> > >         GEN_DEFAULT_PIPEOFFSETS, \
> > >         GEN_DEFAULT_PAGE_SIZES, \
> > >         IVB_CURSOR_OFFSETS
> > > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> > >         .has_hotplug = 1,
> > >         .has_aliasing_ppgtt = 1,
> > >         .has_full_ppgtt = 1,
> > > +       .full_ppgtt_bits = 32,
> > >         .has_snoop = true,
> > >         .has_coherent_ggtt = false,
> > >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> > 
> > To be pedant, .bits = 31 for gen6/7.
> > -Chris
> 
> If I'm reading the code right, these use a different method of setting
> the vm.total so won't use the .full_ppgtt_bits.
> 
> I don't know enough about this, but would it make sense to modify
> gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
> 31) or maybe just not set .full_ppgtt_bits for those platforms or set
> the value correctly and ignore it for now?

One of our goals is to remove the differences where none exist...
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..52bebd67173a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@  void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..a367686fd735 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,7 +2569,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 
 #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..1add339ca6be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -249,7 +249,7 @@  static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..c66bbf409791 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@  int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 			       	int enable_ppgtt)
 {
 	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
+	bool has_full_4lvl_ppgtt;
 
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
 	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
 		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
 	}
 
 	/*
@@ -164,7 +164,7 @@  int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 		return 3;
 
 	/* Disable ppgtt on SNB if VT-d is on. */
@@ -173,7 +173,7 @@  int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (has_full_48bit_ppgtt)
+	if (has_full_4lvl_ppgtt)
 		return 3;
 
 	if (has_full_ppgtt)
@@ -628,14 +628,14 @@  setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -780,7 +780,7 @@  static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1647,9 +1647,9 @@  static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
+	if (i915_modparams.enable_ppgtt < 3)
+		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1788,7 @@  static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@  struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@  static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..e0619952ff52 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -299,6 +299,7 @@  static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
+	.full_ppgtt_bits = 32, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -353,6 +354,7 @@  static const struct intel_device_info intel_valleyview_info = {
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +401,7 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -445,6 +447,7 @@  static const struct intel_device_info intel_cherryview_info = {
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -520,7 +523,7 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..6d2f9f06ab57 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@  enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..180f2dca1223 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@  void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..b830a7b5064f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@ 
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..50acb0463e9a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,7 +88,6 @@  enum intel_platform {
 	func(has_fbc); \
 	func(has_fpga_dbg); \
 	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -182,6 +181,9 @@  struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index def467c2451b..52a86a8c06b7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -429,7 +429,7 @@  static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -2019,7 +2019,7 @@  static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not needed in 48-bit.*/
 	if (rq->gem_context->ppgtt &&
 	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2688,8 +2688,8 @@  static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
-		/* 64b PPGTT (48bit canonical)
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
+		/* > 32b PPGTT
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
 		 */
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..b065630bf672 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1434,8 +1434,8 @@  static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1708,8 +1708,8 @@  int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..33d7225edbbb 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@  struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);