[v2,4/4] drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite planes
diff mbox series

Message ID 1536748369-3624-5-git-send-email-swati2.sharma@intel.com
State New
Headers show
Series
  • Enable Y210, Y212, Y216 formats for ICL
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Commit Message

Swati Sharma Sept. 12, 2018, 10:32 a.m. UTC
From: Vidya Srinivas <vidya.srinivas@intel.com>

In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_sprite.c  | 22 ++++++++++++++++++++--
 2 files changed, 43 insertions(+), 4 deletions(-)

Comments

Juha-Pekka Heikkila Sept. 12, 2018, 1:22 p.m. UTC | #1
On 12.09.2018 13:32, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> In this patch, a list for icl specific pixel formats is created
> in which Y210, Y212 and Y216 pixel formats are added along with
> legacy pixel formats for primary and sprite plane.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++--
>   drivers/gpu/drm/i915/intel_sprite.c  | 22 ++++++++++++++++++++--
>   2 files changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7c68a0d..f341cbd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -105,6 +105,24 @@
>   	DRM_FORMAT_NV12,
>   };
>   
> +static const uint32_t icl_primary_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
>   static const uint64_t skl_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -13725,8 +13743,11 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
>   	if (INTEL_GEN(dev_priv) >= 9) {
>   		primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
>   						     PLANE_PRIMARY);
> -
> -		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> +		if (INTEL_GEN(dev_priv) >= 11) {
> +			intel_primary_formats = icl_primary_formats;
> +			num_formats = ARRAY_SIZE(icl_primary_formats);
> +		} else if (skl_plane_has_planar(dev_priv, pipe,
> +						PLANE_PRIMARY)) {

Above doesn't look right. I think it could be written "if(gen>=11) {...} 
else if(gen>=9){...". Now it looks support for planar formats on ICL is 
totally skipped. As is inside skl_plane_has_planar(..) there's check if 
running on ICL no planar support is available but it is only until 
planar support for ICL is patched in. I suspect you are going to need 
icl_primary_formats[] as well as icl_pri_planar_formats[] in similar way 
as on SKL. It is similar issue below with changes for intel_sprite.c

/Juha-Pekka

>   			intel_primary_formats = skl_pri_planar_formats;
>   			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
>   		} else {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7e2768..2e61fe19 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_NV12,
>   };
>   
> +static uint32_t icl_plane_formats[] = {
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -1536,8 +1551,11 @@ struct intel_plane *
>   		intel_plane->disable_plane = skl_disable_plane;
>   		intel_plane->get_hw_state = skl_plane_get_hw_state;
>   
> -		if (skl_plane_has_planar(dev_priv, pipe,
> -					 PLANE_SPRITE0 + plane)) {
> +		if (INTEL_GEN(dev_priv) >= 11) {
> +			plane_formats = icl_plane_formats;
> +			num_plane_formats = ARRAY_SIZE(icl_plane_formats);
> +		} else if (skl_plane_has_planar(dev_priv, pipe,
> +						PLANE_SPRITE0 + plane)) {
>   			plane_formats = skl_planar_formats;
>   			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
>   		} else {
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7c68a0d..f341cbd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -105,6 +105,24 @@ 
 	DRM_FORMAT_NV12,
 };
 
+static const uint32_t icl_primary_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
 static const uint64_t skl_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -13725,8 +13743,11 @@  bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) >= 9) {
 		primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
 						     PLANE_PRIMARY);
-
-		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+		if (INTEL_GEN(dev_priv) >= 11) {
+			intel_primary_formats = icl_primary_formats;
+			num_formats = ARRAY_SIZE(icl_primary_formats);
+		} else if (skl_plane_has_planar(dev_priv, pipe,
+						PLANE_PRIMARY)) {
 			intel_primary_formats = skl_pri_planar_formats;
 			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
 		} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f7e2768..2e61fe19 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1281,6 +1281,21 @@  int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_NV12,
 };
 
+static uint32_t icl_plane_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1536,8 +1551,11 @@  struct intel_plane *
 		intel_plane->disable_plane = skl_disable_plane;
 		intel_plane->get_hw_state = skl_plane_get_hw_state;
 
-		if (skl_plane_has_planar(dev_priv, pipe,
-					 PLANE_SPRITE0 + plane)) {
+		if (INTEL_GEN(dev_priv) >= 11) {
+			plane_formats = icl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(icl_plane_formats);
+		} else if (skl_plane_has_planar(dev_priv, pipe,
+						PLANE_SPRITE0 + plane)) {
 			plane_formats = skl_planar_formats;
 			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
 		} else {