diff mbox series

[v3,3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC

Message ID 20180918181015.11001-3-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake | expand

Commit Message

Souza, Jose Sept. 18, 2018, 6:10 p.m. UTC 
IPC was only added in SKL+(actually we don't even enable for SKL due
WA) so without this change, driver was writing to a reserved bit.

Also removing the uncessary dev_priv->ipc_enabled = false; as now
gens without IPC will not have IPC enabled.

v2(Rodrigo):
- moved the new handling of WA #0477 to the next patch

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db9b8328275..e2ca04534e23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6117,6 +6117,9 @@  void intel_enable_ipc(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 
+	if (!HAS_IPC(dev_priv))
+		return;
+
 	/* Display WA #0477 WaDisableIPC: skl */
 	if (IS_SKYLAKE(dev_priv))
 		dev_priv->ipc_enabled = false;
@@ -6138,7 +6141,6 @@  void intel_enable_ipc(struct drm_i915_private *dev_priv)
 
 void intel_init_ipc(struct drm_i915_private *dev_priv)
 {
-	dev_priv->ipc_enabled = false;
 	if (!HAS_IPC(dev_priv))
 		return;