diff mbox series

[v4,2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place

Message ID 20180918204714.27306-2-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [v4,1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake | expand

Commit Message

Souza, Jose Sept. 18, 2018, 8:47 p.m. UTC 
Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.

v2(Rodrigo):
- handling IVYBRIDGE case inside intel_pch_reset_handshake()

v4(Rodrigo and Ville):
- moving the enable/disable decision to callers

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         | 12 -----------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++++++++++-------
 2 files changed, 20 insertions(+), 20 deletions(-)

Comments

Rodrigo Vivi Sept. 18, 2018, 9:48 p.m. UTC | #1 
On Tue, Sep 18, 2018 at 01:47:10PM -0700, José Roberto de Souza wrote:
> Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> i915_gem_init_hw().
> So making skl_pch_reset_handshake() handle both cases and calling
> it for the missing gens in intel_power_domains_init_hw().
> Ivybridge have a different register and bits but with the same
> objective so moving it too.
> 
> v2(Rodrigo):
> - handling IVYBRIDGE case inside intel_pch_reset_handshake()
> 
> v4(Rodrigo and Ville):
> - moving the enable/disable decision to callers
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

I was going to cowardly wait for CI, but I will end up
forgetting the review and code looks right to my human eyes,
so before I forget:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem.c         | 12 -----------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++++++++++-------
>  2 files changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a94d5a308c4d..3fe5d4f058ee 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5299,18 +5299,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>  		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>  			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
> -	if (HAS_PCH_NOP(dev_priv)) {
> -		if (IS_IVYBRIDGE(dev_priv)) {
> -			u32 temp = I915_READ(GEN7_MSG_CTL);
> -			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> -			I915_WRITE(GEN7_MSG_CTL, temp);
> -		} else if (INTEL_GEN(dev_priv) >= 7) {
> -			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> -			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> -			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> -		}
> -	}
> -
>  	intel_gt_workarounds_apply(dev_priv);
>  
>  	i915_gem_init_swizzling(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index aa0ff4c08bad..308d06971435 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3242,14 +3242,25 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
>  				      bool enable)
>  {
> -	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +	i915_reg_t reg;
> +	u32 reset_bits, val;
> +
> +	if (IS_IVYBRIDGE(dev_priv)) {
> +		reg = GEN7_MSG_CTL;
> +		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
> +	} else {
> +		reg = HSW_NDE_RSTWRN_OPT;
> +		reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
> +	}
> +
> +	val = I915_READ(reg);
>  
>  	if (enable)
> -		val |= RESET_PCH_HANDSHAKE_ENABLE;
> +		val |= reset_bits;
>  	else
> -		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +		val &= ~reset_bits;
>  
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	I915_WRITE(reg, val);
>  }
>  
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
> @@ -3261,7 +3272,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* enable PCH reset handshake */
> -	intel_pch_reset_handshake(dev_priv, true);
> +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>  
>  	/* enable PG1 and Misc I/O */
>  	mutex_lock(&power_domains->lock);
> @@ -3447,7 +3458,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH Reset Handshake */
> -	intel_pch_reset_handshake(dev_priv, true);
> +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>  
>  	/* 2. Enable Comp */
>  	val = I915_READ(CHICKEN_MISC_2);
> @@ -3530,7 +3541,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH reset handshake. */
> -	intel_pch_reset_handshake(dev_priv, true);
> +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>  
>  	for (port = PORT_A; port <= PORT_B; port++) {
>  		/* 2. Enable DDI combo PHY comp. */
> @@ -3762,7 +3773,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>  		mutex_lock(&power_domains->lock);
>  		vlv_cmnlane_wa(dev_priv);
>  		mutex_unlock(&power_domains->lock);
> -	}
> +	} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> +		intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>  
>  	/*
>  	 * Keep all power wells enabled for any dependent HW access during
> -- 
> 2.19.0
>
Rodrigo Vivi Sept. 27, 2018, 12:15 a.m. UTC | #2 
On Tue, Sep 18, 2018 at 02:48:13PM -0700, Rodrigo Vivi wrote:
> On Tue, Sep 18, 2018 at 01:47:10PM -0700, José Roberto de Souza wrote:
> > Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> > of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> > i915_gem_init_hw().
> > So making skl_pch_reset_handshake() handle both cases and calling
> > it for the missing gens in intel_power_domains_init_hw().
> > Ivybridge have a different register and bits but with the same
> > objective so moving it too.
> > 
> > v2(Rodrigo):
> > - handling IVYBRIDGE case inside intel_pch_reset_handshake()
> > 
> > v4(Rodrigo and Ville):
> > - moving the enable/disable decision to callers
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> 
> I was going to cowardly wait for CI, but I will end up
> forgetting the review and code looks right to my human eyes,
> so before I forget:
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

pushed to dinq. Thanks for the patches.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c         | 12 -----------
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++++++++++-------
> >  2 files changed, 20 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index a94d5a308c4d..3fe5d4f058ee 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -5299,18 +5299,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> >  		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> >  			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >  
> > -	if (HAS_PCH_NOP(dev_priv)) {
> > -		if (IS_IVYBRIDGE(dev_priv)) {
> > -			u32 temp = I915_READ(GEN7_MSG_CTL);
> > -			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> > -			I915_WRITE(GEN7_MSG_CTL, temp);
> > -		} else if (INTEL_GEN(dev_priv) >= 7) {
> > -			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> > -			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > -			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> > -		}
> > -	}
> > -
> >  	intel_gt_workarounds_apply(dev_priv);
> >  
> >  	i915_gem_init_swizzling(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index aa0ff4c08bad..308d06971435 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3242,14 +3242,25 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
> >  static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
> >  				      bool enable)
> >  {
> > -	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > +	i915_reg_t reg;
> > +	u32 reset_bits, val;
> > +
> > +	if (IS_IVYBRIDGE(dev_priv)) {
> > +		reg = GEN7_MSG_CTL;
> > +		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
> > +	} else {
> > +		reg = HSW_NDE_RSTWRN_OPT;
> > +		reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
> > +	}
> > +
> > +	val = I915_READ(reg);
> >  
> >  	if (enable)
> > -		val |= RESET_PCH_HANDSHAKE_ENABLE;
> > +		val |= reset_bits;
> >  	else
> > -		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > +		val &= ~reset_bits;
> >  
> > -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > +	I915_WRITE(reg, val);
> >  }
> >  
> >  static void skl_display_core_init(struct drm_i915_private *dev_priv,
> > @@ -3261,7 +3272,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> >  	/* enable PCH reset handshake */
> > -	intel_pch_reset_handshake(dev_priv, true);
> > +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> >  
> >  	/* enable PG1 and Misc I/O */
> >  	mutex_lock(&power_domains->lock);
> > @@ -3447,7 +3458,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> >  	/* 1. Enable PCH Reset Handshake */
> > -	intel_pch_reset_handshake(dev_priv, true);
> > +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> >  
> >  	/* 2. Enable Comp */
> >  	val = I915_READ(CHICKEN_MISC_2);
> > @@ -3530,7 +3541,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> >  	/* 1. Enable PCH reset handshake. */
> > -	intel_pch_reset_handshake(dev_priv, true);
> > +	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> >  
> >  	for (port = PORT_A; port <= PORT_B; port++) {
> >  		/* 2. Enable DDI combo PHY comp. */
> > @@ -3762,7 +3773,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> >  		mutex_lock(&power_domains->lock);
> >  		vlv_cmnlane_wa(dev_priv);
> >  		mutex_unlock(&power_domains->lock);
> > -	}
> > +	} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> > +		intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> >  
> >  	/*
> >  	 * Keep all power wells enabled for any dependent HW access during
> > -- 
> > 2.19.0
> > 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a94d5a308c4d..3fe5d4f058ee 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5299,18 +5299,6 @@  int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
-	if (HAS_PCH_NOP(dev_priv)) {
-		if (IS_IVYBRIDGE(dev_priv)) {
-			u32 temp = I915_READ(GEN7_MSG_CTL);
-			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
-			I915_WRITE(GEN7_MSG_CTL, temp);
-		} else if (INTEL_GEN(dev_priv) >= 7) {
-			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
-			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
-			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
-		}
-	}
-
 	intel_gt_workarounds_apply(dev_priv);
 
 	i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index aa0ff4c08bad..308d06971435 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3242,14 +3242,25 @@  static void icl_mbus_init(struct drm_i915_private *dev_priv)
 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
 				      bool enable)
 {
-	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	i915_reg_t reg;
+	u32 reset_bits, val;
+
+	if (IS_IVYBRIDGE(dev_priv)) {
+		reg = GEN7_MSG_CTL;
+		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
+	} else {
+		reg = HSW_NDE_RSTWRN_OPT;
+		reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
+	}
+
+	val = I915_READ(reg);
 
 	if (enable)
-		val |= RESET_PCH_HANDSHAKE_ENABLE;
+		val |= reset_bits;
 	else
-		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+		val &= ~reset_bits;
 
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	I915_WRITE(reg, val);
 }
 
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
@@ -3261,7 +3272,7 @@  static void skl_display_core_init(struct drm_i915_private *dev_priv,
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* enable PCH reset handshake */
-	intel_pch_reset_handshake(dev_priv, true);
+	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
@@ -3447,7 +3458,7 @@  static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH Reset Handshake */
-	intel_pch_reset_handshake(dev_priv, true);
+	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
 	/* 2. Enable Comp */
 	val = I915_READ(CHICKEN_MISC_2);
@@ -3530,7 +3541,7 @@  static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH reset handshake. */
-	intel_pch_reset_handshake(dev_priv, true);
+	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
 	for (port = PORT_A; port <= PORT_B; port++) {
 		/* 2. Enable DDI combo PHY comp. */
@@ -3762,7 +3773,8 @@  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 		mutex_lock(&power_domains->lock);
 		vlv_cmnlane_wa(dev_priv);
 		mutex_unlock(&power_domains->lock);
-	}
+	} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
+		intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
 	/*
 	 * Keep all power wells enabled for any dependent HW access during