[v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
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Message ID 20180925052151.9537-1-vigneshr@ti.com
State New
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Series
  • [v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
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Commit Message

Vignesh Raghavendra Sept. 25, 2018, 5:21 a.m. UTC
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.

Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
---

This patch is split from v3 here:
https://lore.kernel.org/patchwork/cover/967020/
Patch can be applied standalone and has no dependencies on other patches
in v3.

 arch/arm/boot/dts/dra7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Tony Lindgren Sept. 26, 2018, 5:27 p.m. UTC | #1
* Vignesh R <vigneshr@ti.com> [180924 22:25]:
> Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
> PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
> incorrectly documented in the TRM. In fact, the bit positions are
> swapped. Update the DT bindings for PCIe EP to reflect the same.
> 
> Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
> Cc: stable@vger.kernel.org
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> 
> This patch is split from v3 here:
> https://lore.kernel.org/patchwork/cover/967020/
> Patch can be applied standalone and has no dependencies on other patches
> in v3.

Hmm is this needed for v4.19-rc cycle or can this wait for
v4.20 merge window?

Regards,

Tony
Vignesh Raghavendra Sept. 28, 2018, 5:28 a.m. UTC | #2
On Wednesday 26 September 2018 10:57 PM, Tony Lindgren wrote:
> * Vignesh R <vigneshr@ti.com> [180924 22:25]:
>> Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
>> PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
>> incorrectly documented in the TRM. In fact, the bit positions are
>> swapped. Update the DT bindings for PCIe EP to reflect the same.
>>
>> Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>
>> This patch is split from v3 here:
>> https://lore.kernel.org/patchwork/cover/967020/
>> Patch can be applied standalone and has no dependencies on other patches
>> in v3.
> 
> Hmm is this needed for v4.19-rc cycle or can this wait for
> v4.20 merge window?
> 

v4.20 should be fine.
Tony Lindgren Sept. 28, 2018, 5:26 p.m. UTC | #3
* Vignesh R <vigneshr@ti.com> [180928 05:31]:
> 
> 
> On Wednesday 26 September 2018 10:57 PM, Tony Lindgren wrote:
> > * Vignesh R <vigneshr@ti.com> [180924 22:25]:
> >> Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
> >> PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
> >> incorrectly documented in the TRM. In fact, the bit positions are
> >> swapped. Update the DT bindings for PCIe EP to reflect the same.
> >>
> >> Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
> >> Cc: stable@vger.kernel.org
> >> Signed-off-by: Vignesh R <vigneshr@ti.com>
> >> ---
> >>
> >> This patch is split from v3 here:
> >> https://lore.kernel.org/patchwork/cover/967020/
> >> Patch can be applied standalone and has no dependencies on other patches
> >> in v3.
> > 
> > Hmm is this needed for v4.19-rc cycle or can this wait for
> > v4.20 merge window?
> > 
> 
> v4.20 should be fine.

OK thanks applying into omap-for-v4.20/dt then.

Tony

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1050da6c6d35..fc50d6a8e51a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -355,7 +355,7 @@ 
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
-				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+				ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 				status = "disabled";
 			};
 		};