diff mbox series

[v2,5/7] arm64:dts:sdm845: Add register range for gpu CX

Message ID 1538744915-25490-6-git-send-email-smasetty@codeaurora.org (mailing list archive)
State Not Applicable, archived
Delegated to: Andy Gross
Headers show
Series drm/msm/a6xx: System Cache Support | expand

Commit Message

Sharat Masetty Oct. 5, 2018, 1:08 p.m. UTC 
This patch adds a register range in the gpu CX domain. This is needed to
support the last level system cache(LLC).

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 720b734..e106f26 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2780,8 +2780,8 @@ 
 			compatible = "qcom,adreno-630.2", "qcom,adreno";
 			#stream-id-cells = <16>;
 
-			reg = <0x5000000 0x40000>;
-			reg-names = "kgsl_3d0_reg_memory";
+			reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
 
 			/*
 			 * Look ma, no clocks! The GPU clocks and power are