[02/10] drm/i915: Make intel_dp_set_m_n take crtc_state

Message ID	20181011100457.8776-3-maarten.lankhorst@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Oct 2018 12:04:49 +0200 Message-Id: <20181011100457.8776-3-maarten.lankhorst@linux.intel.com> In-Reply-To: <20181011100457.8776-1-maarten.lankhorst@linux.intel.com> References: <20181011100457.8776-1-maarten.lankhorst@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/10] drm/i915: Make intel_dp_set_m_n take crtc_state Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: Remove low hanging crtc->config fruit, part 2. \| expand [00/10] drm/i915: Remove low hanging crtc->config fruit, part 2. [01/10] drm/i915: Remove crtc->config dereference from drrs_ctl [02/10] drm/i915: Make intel_dp_set_m_n take crtc_state [03/10] drm/i915: Remove crtc->config references in vlv_prepare_pll [04/10] drm/i915: Always read out M2_N2 in intel_cpu_transcoder_get_m_n [05/10] drm/i915: Pass crtc_state to update_scanline_offset [06/10] drm/i915: Remove crtc->config dereferences in intel_sanitize_crtc [07/10] drm/i915: Remove crtc->config dereferences in intel_modeset_setup_hw_state [08/10] drm/i915: Pass crtc_state to lpt_program_iclkip [09/10] drm/i915: Pass crtc_state to ivybridge_update_fdi_bc_bifurcation [10/10] drm/i915: Remove crtc->active from crtc_enable callbacks

Message ID

20181011100457.8776-3-maarten.lankhorst@linux.intel.com (mailing list archive)

State

New, archived

Headers

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Thu, 11 Oct 2018 12:04:49 +0200
Message-Id: <20181011100457.8776-3-maarten.lankhorst@linux.intel.com>
In-Reply-To: <20181011100457.8776-1-maarten.lankhorst@linux.intel.com>
References: <20181011100457.8776-1-maarten.lankhorst@linux.intel.com>
MIME-Version: 1.0
Subject: [Intel-gfx] [PATCH 02/10] drm/i915: Make intel_dp_set_m_n take
 crtc_state
Precedence: list
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Series

drm/i915: Remove low hanging crtc->config fruit, part 2. | expand

Commit Message

Maarten Lankhorst Oct. 11, 2018, 10:04 a.m. UTC

Another user of crtc->config gone. The functions it calls also
needed crtc->config, so convert those as well.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++--------------
 drivers/gpu/drm/i915/intel_dp.c      |  4 +-
 drivers/gpu/drm/i915/intel_drv.h     |  3 +-
 3 files changed, 35 insertions(+), 33 deletions(-)

Comments

Ville Syrjälä Oct. 11, 2018, 11:39 a.m. UTC | #1

On Thu, Oct 11, 2018 at 12:04:49PM +0200, Maarten Lankhorst wrote:
> Another user of crtc->config gone. The functions it calls also
> needed crtc->config, so convert those as well.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_dp.c      |  4 +-
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +-
>  3 files changed, 35 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3fd37a9fd49..3d3eefa6ec65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -143,9 +143,9 @@ static int intel_framebuffer_init(struct intel_framebuffer *ifb,
>  				  struct drm_mode_fb_cmd2 *mode_cmd);
>  static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> -					 struct intel_link_m_n *m_n,
> -					 struct intel_link_m_n *m2_n2);
> +static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> +					 const struct intel_link_m_n *m_n,
> +					 const struct intel_link_m_n *m2_n2);
>  static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
>  static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
>  static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
> @@ -5604,14 +5604,14 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  		intel_prepare_shared_dpll(pipe_config);
>  
>  	if (intel_crtc_has_dp_encoder(pipe_config))
> -		intel_dp_set_m_n(intel_crtc, M1_N1);
> +		intel_dp_set_m_n(pipe_config, M1_N1);
>  
>  	intel_set_pipe_timings(pipe_config);
>  	intel_set_pipe_src_size(pipe_config);
>  
>  	if (pipe_config->has_pch_encoder) {
> -		intel_cpu_transcoder_set_m_n(intel_crtc,
> -				     &pipe_config->fdi_m_n, NULL);
> +		intel_cpu_transcoder_set_m_n(pipe_config,
> +					     &pipe_config->fdi_m_n, NULL);
>  	}
>  
>  	ironlake_set_pipeconf(pipe_config);
> @@ -5728,7 +5728,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	intel_encoders_pre_enable(crtc, pipe_config, old_state);
>  
>  	if (intel_crtc_has_dp_encoder(pipe_config))
> -		intel_dp_set_m_n(intel_crtc, M1_N1);
> +		intel_dp_set_m_n(pipe_config, M1_N1);
>  
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_set_pipe_timings(pipe_config);
> @@ -5742,8 +5742,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	}
>  
>  	if (pipe_config->has_pch_encoder) {
> -		intel_cpu_transcoder_set_m_n(intel_crtc,
> -				     &pipe_config->fdi_m_n, NULL);
> +		intel_cpu_transcoder_set_m_n(pipe_config,
> +					     &pipe_config->fdi_m_n, NULL);
>  	}
>  
>  	if (!transcoder_is_dsi(cpu_transcoder))
> @@ -6070,7 +6070,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  		return;
>  
>  	if (intel_crtc_has_dp_encoder(pipe_config))
> -		intel_dp_set_m_n(intel_crtc, M1_N1);
> +		intel_dp_set_m_n(pipe_config, M1_N1);
>  
>  	intel_set_pipe_timings(pipe_config);
>  	intel_set_pipe_src_size(pipe_config);
> @@ -6140,7 +6140,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  	i9xx_set_pll_dividers(pipe_config);
>  
>  	if (intel_crtc_has_dp_encoder(pipe_config))
> -		intel_dp_set_m_n(intel_crtc, M1_N1);
> +		intel_dp_set_m_n(pipe_config, M1_N1);
>  
>  	intel_set_pipe_timings(pipe_config);
>  	intel_set_pipe_src_size(pipe_config);
> @@ -6865,12 +6865,12 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
>  	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
>  }
>  
> -static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
> -					 struct intel_link_m_n *m_n)
> +static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state)

I'd probably still pass the m_n struct in explicity here as there's
nothing in the function name that says "this is for dp only".

Apart from that lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int pipe = crtc->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
> +	enum pipe pipe = crtc->pipe;
>  
>  	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
>  	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
> @@ -6878,13 +6878,14 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
>  	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
>  }
>  
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> -					 struct intel_link_m_n *m_n,
> -					 struct intel_link_m_n *m2_n2)
> +static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> +					 const struct intel_link_m_n *m_n,
> +					 const struct intel_link_m_n *m2_n2)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int pipe = crtc->pipe;
> -	enum transcoder transcoder = crtc->config->cpu_transcoder;
> +	enum pipe pipe = crtc->pipe;
> +	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
>  	if (INTEL_GEN(dev_priv) >= 5) {
>  		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
> @@ -6896,7 +6897,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>  		 * registers are not unnecessarily accessed).
>  		 */
>  		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
> -		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
> +		    INTEL_GEN(dev_priv) < 8) && crtc_state->has_drrs) {
>  			I915_WRITE(PIPE_DATA_M2(transcoder),
>  					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
>  			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -6911,29 +6912,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>  	}
>  }
>  
> -void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
> +void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
>  {
> -	struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
> +	const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
>  
>  	if (m_n == M1_N1) {
> -		dp_m_n = &crtc->config->dp_m_n;
> -		dp_m2_n2 = &crtc->config->dp_m2_n2;
> +		dp_m_n = &crtc_state->dp_m_n;
> +		dp_m2_n2 = &crtc_state->dp_m2_n2;
>  	} else if (m_n == M2_N2) {
>  
>  		/*
>  		 * M2_N2 registers are not supported. Hence m2_n2 divider value
>  		 * needs to be programmed into M1_N1.
>  		 */
> -		dp_m_n = &crtc->config->dp_m2_n2;
> +		dp_m_n = &crtc_state->dp_m2_n2;
>  	} else {
>  		DRM_ERROR("Unsupported divider value\n");
>  		return;
>  	}
>  
> -	if (crtc->config->has_pch_encoder)
> -		intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
> +	if (crtc_state->has_pch_encoder)
> +		intel_pch_transcoder_set_m_n(crtc_state);
>  	else
> -		intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
> +		intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
>  }
>  
>  static void vlv_compute_dpll(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 19f0c3f59cbe..21bb7c8cb721 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6082,10 +6082,10 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>  	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
>  		switch (index) {
>  		case DRRS_HIGH_RR:
> -			intel_dp_set_m_n(intel_crtc, M1_N1);
> +			intel_dp_set_m_n(crtc_state, M1_N1);
>  			break;
>  		case DRRS_LOW_RR:
> -			intel_dp_set_m_n(intel_crtc, M2_N2);
> +			intel_dp_set_m_n(crtc_state, M2_N2);
>  			break;
>  		case DRRS_MAX_RR:
>  		default:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 43190c6e9ef2..9d29c414628b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1627,7 +1627,8 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
> -void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> +void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> +		      enum link_m_n_set m_n);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
>  			struct dpll *best_clock);
> -- 
> 2.19.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3fd37a9fd49..3d3eefa6ec65 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -143,9 +143,9 @@  static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 				  struct drm_mode_fb_cmd2 *mode_cmd);
 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n,
-					 struct intel_link_m_n *m2_n2);
+static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
+					 const struct intel_link_m_n *m_n,
+					 const struct intel_link_m_n *m2_n2);
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
@@ -5604,14 +5604,14 @@  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 		intel_prepare_shared_dpll(pipe_config);
 
 	if (intel_crtc_has_dp_encoder(pipe_config))
-		intel_dp_set_m_n(intel_crtc, M1_N1);
+		intel_dp_set_m_n(pipe_config, M1_N1);
 
 	intel_set_pipe_timings(pipe_config);
 	intel_set_pipe_src_size(pipe_config);
 
 	if (pipe_config->has_pch_encoder) {
-		intel_cpu_transcoder_set_m_n(intel_crtc,
-				     &pipe_config->fdi_m_n, NULL);
+		intel_cpu_transcoder_set_m_n(pipe_config,
+					     &pipe_config->fdi_m_n, NULL);
 	}
 
 	ironlake_set_pipeconf(pipe_config);
@@ -5728,7 +5728,7 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc_has_dp_encoder(pipe_config))
-		intel_dp_set_m_n(intel_crtc, M1_N1);
+		intel_dp_set_m_n(pipe_config, M1_N1);
 
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_set_pipe_timings(pipe_config);
@@ -5742,8 +5742,8 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	}
 
 	if (pipe_config->has_pch_encoder) {
-		intel_cpu_transcoder_set_m_n(intel_crtc,
-				     &pipe_config->fdi_m_n, NULL);
+		intel_cpu_transcoder_set_m_n(pipe_config,
+					     &pipe_config->fdi_m_n, NULL);
 	}
 
 	if (!transcoder_is_dsi(cpu_transcoder))
@@ -6070,7 +6070,7 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 		return;
 
 	if (intel_crtc_has_dp_encoder(pipe_config))
-		intel_dp_set_m_n(intel_crtc, M1_N1);
+		intel_dp_set_m_n(pipe_config, M1_N1);
 
 	intel_set_pipe_timings(pipe_config);
 	intel_set_pipe_src_size(pipe_config);
@@ -6140,7 +6140,7 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	i9xx_set_pll_dividers(pipe_config);
 
 	if (intel_crtc_has_dp_encoder(pipe_config))
-		intel_dp_set_m_n(intel_crtc, M1_N1);
+		intel_dp_set_m_n(pipe_config, M1_N1);
 
 	intel_set_pipe_timings(pipe_config);
 	intel_set_pipe_src_size(pipe_config);
@@ -6865,12 +6865,12 @@  static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
 	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
 }
 
-static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n)
+static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	int pipe = crtc->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+	enum pipe pipe = crtc->pipe;
 
 	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
 	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
@@ -6878,13 +6878,14 @@  static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
 	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
 }
 
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n,
-					 struct intel_link_m_n *m2_n2)
+static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
+					 const struct intel_link_m_n *m_n,
+					 const struct intel_link_m_n *m2_n2)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int pipe = crtc->pipe;
-	enum transcoder transcoder = crtc->config->cpu_transcoder;
+	enum pipe pipe = crtc->pipe;
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
 	if (INTEL_GEN(dev_priv) >= 5) {
 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
@@ -6896,7 +6897,7 @@  static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 		 * registers are not unnecessarily accessed).
 		 */
 		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
-		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
+		    INTEL_GEN(dev_priv) < 8) && crtc_state->has_drrs) {
 			I915_WRITE(PIPE_DATA_M2(transcoder),
 					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -6911,29 +6912,29 @@  static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 	}
 }
 
-void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
+void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
 {
-	struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+	const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
 
 	if (m_n == M1_N1) {
-		dp_m_n = &crtc->config->dp_m_n;
-		dp_m2_n2 = &crtc->config->dp_m2_n2;
+		dp_m_n = &crtc_state->dp_m_n;
+		dp_m2_n2 = &crtc_state->dp_m2_n2;
 	} else if (m_n == M2_N2) {
 
 		/*
 		 * M2_N2 registers are not supported. Hence m2_n2 divider value
 		 * needs to be programmed into M1_N1.
 		 */
-		dp_m_n = &crtc->config->dp_m2_n2;
+		dp_m_n = &crtc_state->dp_m2_n2;
 	} else {
 		DRM_ERROR("Unsupported divider value\n");
 		return;
 	}
 
-	if (crtc->config->has_pch_encoder)
-		intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
+	if (crtc_state->has_pch_encoder)
+		intel_pch_transcoder_set_m_n(crtc_state);
 	else
-		intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
+		intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
 }
 
 static void vlv_compute_dpll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 19f0c3f59cbe..21bb7c8cb721 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6082,10 +6082,10 @@  static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
 		switch (index) {
 		case DRRS_HIGH_RR:
-			intel_dp_set_m_n(intel_crtc, M1_N1);
+			intel_dp_set_m_n(crtc_state, M1_N1);
 			break;
 		case DRRS_LOW_RR:
-			intel_dp_set_m_n(intel_crtc, M2_N2);
+			intel_dp_set_m_n(crtc_state, M2_N2);
 			break;
 		case DRRS_MAX_RR:
 		default:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 43190c6e9ef2..9d29c414628b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,7 +1627,8 @@  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
+void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
+		      enum link_m_n_set m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 			struct dpll *best_clock);

[02/10] drm/i915: Make intel_dp_set_m_n take crtc_state

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