| Message ID | 20181018115134.9061-7-maarten.lankhorst@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gen11: Add support for the NV12 format. | expand |
On Thu, Oct 18, 2018 at 01:51:32PM +0200, Maarten Lankhorst wrote: > We configure the chroma upsampler with the same chroma siting as > used by the scaler for consistency, the chroma upsampler is used > instead of the scaler for YUV 4:2:0 on ICL's HDR planes. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > --- > Can't test this completely until we have correct colors by programming > the input CSC, but should be easy to fix the phases afterwards.. Aye. The current numbers can make sense, but testing would be nice indeed. But as you say it's easy to change later. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++++ > 2 files changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8a81e7c2fe25..17b38ccbff6e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6524,6 +6524,19 @@ enum { > #define _PLANE_AUX_DIST_2_A 0x702c0 > #define _PLANE_AUX_OFFSET_1_A 0x701c4 > #define _PLANE_AUX_OFFSET_2_A 0x702c4 > +#define _PLANE_CUS_CTL_1_A 0x701c8 > +#define _PLANE_CUS_CTL_2_A 0x702c8 > +#define PLANE_CUS_ENABLE (1 << 31) > +#define PLANE_CUS_PLANE_6 (0 << 30) > +#define PLANE_CUS_PLANE_7 (1 << 30) > +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) > +#define PLANE_CUS_HPHASE_0 (0 << 16) > +#define PLANE_CUS_HPHASE_0_25 (1 << 16) > +#define PLANE_CUS_HPHASE_0_5 (2 << 16) > +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) > +#define PLANE_CUS_VPHASE_0 (0 << 12) > +#define PLANE_CUS_VPHASE_0_25 (1 << 12) > +#define PLANE_CUS_VPHASE_0_5 (2 << 12) > #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ > #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ > @@ -6661,6 +6674,15 @@ enum { > #define PLANE_AUX_OFFSET(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) > > +#define _PLANE_CUS_CTL_1_B 0x711c8 > +#define _PLANE_CUS_CTL_2_B 0x712c8 > +#define _PLANE_CUS_CTL_1(pipe) \ > + _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) > +#define _PLANE_CUS_CTL_2(pipe) \ > + _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) > +#define PLANE_CUS_CTL(pipe, plane) \ > + _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) > + > #define _PLANE_COLOR_CTL_1_B 0x711CC > #define _PLANE_COLOR_CTL_2_B 0x712CC > #define _PLANE_COLOR_CTL_3_B 0x713CC > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index a2a4328107b6..2ec5c5df0d24 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -380,6 +380,7 @@ skl_update_plane(struct intel_plane *plane, > uint32_t y = plane_state->color_plane[0].y; > uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; > uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; > + struct intel_plane *linked = plane_state->linked_plane; > unsigned long irqflags; > u32 keymsk = 0, keymax = 0; > > @@ -417,6 +418,27 @@ skl_update_plane(struct intel_plane *plane, > (plane_state->color_plane[1].y << 16) | > plane_state->color_plane[1].x); > > + if (icl_is_hdr_plane(plane)) { > + u32 cus_ctl = 0; > + > + if (linked) { > + /* Enable and use MPEG-2 chroma siting */ > + cus_ctl = PLANE_CUS_ENABLE | > + PLANE_CUS_HPHASE_0 | > + PLANE_CUS_VPHASE_SIGN_NEGATIVE | > + PLANE_CUS_VPHASE_0_25; > + > + if (linked->id == PLANE_SPRITE5) > + cus_ctl |= PLANE_CUS_PLANE_7; > + else if (linked->id == PLANE_SPRITE4) > + cus_ctl |= PLANE_CUS_PLANE_6; > + else > + MISSING_CASE(linked->id); > + } > + > + I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl); > + } > + > /* program plane scaler */ > if (plane_state->scaler_id >= 0) { > skl_program_scaler(dev_priv, plane, crtc_state, plane_state); > -- > 2.19.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8a81e7c2fe25..17b38ccbff6e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6524,6 +6524,19 @@ enum { #define _PLANE_AUX_DIST_2_A 0x702c0 #define _PLANE_AUX_OFFSET_1_A 0x701c4 #define _PLANE_AUX_OFFSET_2_A 0x702c4 +#define _PLANE_CUS_CTL_1_A 0x701c8 +#define _PLANE_CUS_CTL_2_A 0x702c8 +#define PLANE_CUS_ENABLE (1 << 31) +#define PLANE_CUS_PLANE_6 (0 << 30) +#define PLANE_CUS_PLANE_7 (1 << 30) +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) +#define PLANE_CUS_HPHASE_0 (0 << 16) +#define PLANE_CUS_HPHASE_0_25 (1 << 16) +#define PLANE_CUS_HPHASE_0_5 (2 << 16) +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) +#define PLANE_CUS_VPHASE_0 (0 << 12) +#define PLANE_CUS_VPHASE_0_25 (1 << 12) +#define PLANE_CUS_VPHASE_0_5 (2 << 12) #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ @@ -6661,6 +6674,15 @@ enum { #define PLANE_AUX_OFFSET(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) +#define _PLANE_CUS_CTL_1_B 0x711c8 +#define _PLANE_CUS_CTL_2_B 0x712c8 +#define _PLANE_CUS_CTL_1(pipe) \ + _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) +#define _PLANE_CUS_CTL_2(pipe) \ + _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) +#define PLANE_CUS_CTL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) + #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC #define _PLANE_COLOR_CTL_3_B 0x713CC diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index a2a4328107b6..2ec5c5df0d24 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -380,6 +380,7 @@ skl_update_plane(struct intel_plane *plane, uint32_t y = plane_state->color_plane[0].y; uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; + struct intel_plane *linked = plane_state->linked_plane; unsigned long irqflags; u32 keymsk = 0, keymax = 0; @@ -417,6 +418,27 @@ skl_update_plane(struct intel_plane *plane, (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); + if (icl_is_hdr_plane(plane)) { + u32 cus_ctl = 0; + + if (linked) { + /* Enable and use MPEG-2 chroma siting */ + cus_ctl = PLANE_CUS_ENABLE | + PLANE_CUS_HPHASE_0 | + PLANE_CUS_VPHASE_SIGN_NEGATIVE | + PLANE_CUS_VPHASE_0_25; + + if (linked->id == PLANE_SPRITE5) + cus_ctl |= PLANE_CUS_PLANE_7; + else if (linked->id == PLANE_SPRITE4) + cus_ctl |= PLANE_CUS_PLANE_6; + else + MISSING_CASE(linked->id); + } + + I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl); + } + /* program plane scaler */ if (plane_state->scaler_id >= 0) { skl_program_scaler(dev_priv, plane, crtc_state, plane_state);
We configure the chroma upsampler with the same chroma siting as used by the scaler for consistency, the chroma upsampler is used instead of the scaler for YUV 4:2:0 on ICL's HDR planes. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- Can't test this completely until we have correct colors by programming the input CSC, but should be easy to fix the phases afterwards.. drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++++ 2 files changed, 44 insertions(+)