Message ID | 1539867599-20504-4-git-send-email-yael.chemla@foss.arm.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Herbert Xu |
Headers | show |
Series | crypto: ccree: add SM3 support | expand |
Hi Yael, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on crypto/master] [also build test WARNING on v4.19-rc8 next-20181018] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Yael-Chemla/crypto-ccree-add-SM3-support/20181019-042354 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git master config: i386-randconfig-x019-201841 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): drivers/crypto/ccree/cc_hash.c:1729:17: error: 'CC_HW_REV_713' undeclared here (not in a function); did you mean 'CC_HW_REV_712'? .min_hw_rev = CC_HW_REV_713, ^~~~~~~~~~~~~ CC_HW_REV_712 drivers/crypto/ccree/cc_hash.c: In function 'cc_init_hash_sram': drivers/crypto/ccree/cc_hash.c:1832:40: warning: comparison between pointer and integer bool sm3_supported = (drvdata->hw_rev >= CC_HW_REV_713); ^~ In file included from include/linux/kernel.h:10:0, from drivers/crypto/ccree/cc_hash.c:4: drivers/crypto/ccree/cc_hash.c: In function 'cc_hash_alloc': drivers/crypto/ccree/cc_hash.c:1975:22: warning: comparison between pointer and integer if (drvdata->hw_rev >= CC_HW_REV_713) ^ include/linux/compiler.h:58:30: note: in definition of macro '__trace_if' if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ^~~~ >> drivers/crypto/ccree/cc_hash.c:1975:2: note: in expansion of macro 'if' if (drvdata->hw_rev >= CC_HW_REV_713) ^~ drivers/crypto/ccree/cc_hash.c:1975:22: warning: comparison between pointer and integer if (drvdata->hw_rev >= CC_HW_REV_713) ^ include/linux/compiler.h:58:42: note: in definition of macro '__trace_if' if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ^~~~ >> drivers/crypto/ccree/cc_hash.c:1975:2: note: in expansion of macro 'if' if (drvdata->hw_rev >= CC_HW_REV_713) ^~ drivers/crypto/ccree/cc_hash.c:1975:22: warning: comparison between pointer and integer if (drvdata->hw_rev >= CC_HW_REV_713) ^ include/linux/compiler.h:69:16: note: in definition of macro '__trace_if' ______r = !!(cond); \ ^~~~ >> drivers/crypto/ccree/cc_hash.c:1975:2: note: in expansion of macro 'if' if (drvdata->hw_rev >= CC_HW_REV_713) ^~ drivers/crypto/ccree/cc_hash.c: In function 'cc_larval_digest_addr': drivers/crypto/ccree/cc_hash.c:2252:41: warning: comparison between pointer and integer bool sm3_supported = (_drvdata->hw_rev >= CC_HW_REV_713); ^~ vim +/if +1975 drivers/crypto/ccree/cc_hash.c 1952 1953 int cc_hash_alloc(struct cc_drvdata *drvdata) 1954 { 1955 struct cc_hash_handle *hash_handle; 1956 cc_sram_addr_t sram_buff; 1957 u32 sram_size_to_alloc; 1958 struct device *dev = drvdata_to_dev(drvdata); 1959 int rc = 0; 1960 int alg; 1961 1962 hash_handle = kzalloc(sizeof(*hash_handle), GFP_KERNEL); 1963 if (!hash_handle) 1964 return -ENOMEM; 1965 1966 INIT_LIST_HEAD(&hash_handle->hash_list); 1967 drvdata->hash_handle = hash_handle; 1968 1969 sram_size_to_alloc = sizeof(digest_len_init) + 1970 sizeof(md5_init) + 1971 sizeof(sha1_init) + 1972 sizeof(sha224_init) + 1973 sizeof(sha256_init); 1974 > 1975 if (drvdata->hw_rev >= CC_HW_REV_713) 1976 sram_size_to_alloc += sizeof(sm3_init); 1977 1978 if (drvdata->hw_rev >= CC_HW_REV_712) 1979 sram_size_to_alloc += sizeof(digest_len_sha512_init) + 1980 sizeof(sha384_init) + sizeof(sha512_init); 1981 1982 sram_buff = cc_sram_alloc(drvdata, sram_size_to_alloc); 1983 if (sram_buff == NULL_SRAM_ADDR) { 1984 dev_err(dev, "SRAM pool exhausted\n"); 1985 rc = -ENOMEM; 1986 goto fail; 1987 } 1988 1989 /* The initial digest-len offset */ 1990 hash_handle->digest_len_sram_addr = sram_buff; 1991 1992 /*must be set before the alg registration as it is being used there*/ 1993 rc = cc_init_hash_sram(drvdata); 1994 if (rc) { 1995 dev_err(dev, "Init digest CONST failed (rc=%d)\n", rc); 1996 goto fail; 1997 } 1998 1999 /* ahash registration */ 2000 for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { 2001 struct cc_hash_alg *t_alg; 2002 int hw_mode = driver_hash[alg].hw_mode; 2003 2004 /* We either support both HASH and MAC or none */ 2005 if (driver_hash[alg].min_hw_rev > drvdata->hw_rev) 2006 continue; 2007 if (driver_hash[alg].is_mac) { 2008 /* register hmac version */ 2009 t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true); 2010 if (IS_ERR(t_alg)) { 2011 rc = PTR_ERR(t_alg); 2012 dev_err(dev, "%s alg allocation failed\n", 2013 driver_hash[alg].driver_name); 2014 goto fail; 2015 } 2016 t_alg->drvdata = drvdata; 2017 2018 rc = crypto_register_ahash(&t_alg->ahash_alg); 2019 if (rc) { 2020 dev_err(dev, "%s alg registration failed\n", 2021 driver_hash[alg].driver_name); 2022 kfree(t_alg); 2023 goto fail; 2024 } else { 2025 list_add_tail(&t_alg->entry, 2026 &hash_handle->hash_list); 2027 } 2028 } 2029 if (hw_mode == DRV_CIPHER_XCBC_MAC || 2030 hw_mode == DRV_CIPHER_CMAC) 2031 continue; 2032 2033 /* register hash version */ 2034 t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, false); 2035 if (IS_ERR(t_alg)) { 2036 rc = PTR_ERR(t_alg); 2037 dev_err(dev, "%s alg allocation failed\n", 2038 driver_hash[alg].driver_name); 2039 goto fail; 2040 } 2041 t_alg->drvdata = drvdata; 2042 2043 rc = crypto_register_ahash(&t_alg->ahash_alg); 2044 if (rc) { 2045 dev_err(dev, "%s alg registration failed\n", 2046 driver_hash[alg].driver_name); 2047 kfree(t_alg); 2048 goto fail; 2049 } else { 2050 list_add_tail(&t_alg->entry, &hash_handle->hash_list); 2051 } 2052 } 2053 2054 return 0; 2055 2056 fail: 2057 kfree(drvdata->hash_handle); 2058 drvdata->hash_handle = NULL; 2059 return rc; 2060 } 2061 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Yael, Thank you for the patch! Yet something to improve: [auto build test ERROR on crypto/master] [also build test ERROR on v4.19-rc8 next-20181018] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Yael-Chemla/crypto-ccree-add-SM3-support/20181019-042354 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git master config: x86_64-randconfig-s1-10190647 (attached as .config) compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): >> drivers/crypto/ccree/cc_hash.c:1729:17: error: 'CC_HW_REV_713' undeclared here (not in a function) .min_hw_rev = CC_HW_REV_713, ^~~~~~~~~~~~~ drivers/crypto/ccree/cc_hash.c: In function 'cc_init_hash_sram': drivers/crypto/ccree/cc_hash.c:1832:40: warning: comparison between pointer and integer bool sm3_supported = (drvdata->hw_rev >= CC_HW_REV_713); ^~ drivers/crypto/ccree/cc_hash.c: In function 'cc_hash_alloc': drivers/crypto/ccree/cc_hash.c:1975:22: warning: comparison between pointer and integer if (drvdata->hw_rev >= CC_HW_REV_713) ^~ drivers/crypto/ccree/cc_hash.c: In function 'cc_larval_digest_addr': drivers/crypto/ccree/cc_hash.c:2252:41: warning: comparison between pointer and integer bool sm3_supported = (_drvdata->hw_rev >= CC_HW_REV_713); ^~ vim +/CC_HW_REV_713 +1729 drivers/crypto/ccree/cc_hash.c 1543 1544 #define CC_STATE_SIZE(_x) \ 1545 ((_x) + HASH_MAX_LEN_SIZE + CC_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32))) 1546 1547 /* hash descriptors */ 1548 static struct cc_hash_template driver_hash[] = { 1549 //Asynchronize hash template 1550 { 1551 .name = "sha1", 1552 .driver_name = "sha1-ccree", 1553 .mac_name = "hmac(sha1)", 1554 .mac_driver_name = "hmac-sha1-ccree", 1555 .blocksize = SHA1_BLOCK_SIZE, 1556 .is_mac = true, 1557 .synchronize = false, 1558 .template_ahash = { 1559 .init = cc_hash_init, 1560 .update = cc_hash_update, 1561 .final = cc_hash_final, 1562 .finup = cc_hash_finup, 1563 .digest = cc_hash_digest, 1564 .export = cc_hash_export, 1565 .import = cc_hash_import, 1566 .setkey = cc_hash_setkey, 1567 .halg = { 1568 .digestsize = SHA1_DIGEST_SIZE, 1569 .statesize = CC_STATE_SIZE(SHA1_DIGEST_SIZE), 1570 }, 1571 }, 1572 .hash_mode = DRV_HASH_SHA1, 1573 .hw_mode = DRV_HASH_HW_SHA1, 1574 .inter_digestsize = SHA1_DIGEST_SIZE, 1575 .min_hw_rev = CC_HW_REV_630, 1576 }, 1577 { 1578 .name = "sha256", 1579 .driver_name = "sha256-ccree", 1580 .mac_name = "hmac(sha256)", 1581 .mac_driver_name = "hmac-sha256-ccree", 1582 .blocksize = SHA256_BLOCK_SIZE, 1583 .is_mac = true, 1584 .template_ahash = { 1585 .init = cc_hash_init, 1586 .update = cc_hash_update, 1587 .final = cc_hash_final, 1588 .finup = cc_hash_finup, 1589 .digest = cc_hash_digest, 1590 .export = cc_hash_export, 1591 .import = cc_hash_import, 1592 .setkey = cc_hash_setkey, 1593 .halg = { 1594 .digestsize = SHA256_DIGEST_SIZE, 1595 .statesize = CC_STATE_SIZE(SHA256_DIGEST_SIZE) 1596 }, 1597 }, 1598 .hash_mode = DRV_HASH_SHA256, 1599 .hw_mode = DRV_HASH_HW_SHA256, 1600 .inter_digestsize = SHA256_DIGEST_SIZE, 1601 .min_hw_rev = CC_HW_REV_630, 1602 }, 1603 { 1604 .name = "sha224", 1605 .driver_name = "sha224-ccree", 1606 .mac_name = "hmac(sha224)", 1607 .mac_driver_name = "hmac-sha224-ccree", 1608 .blocksize = SHA224_BLOCK_SIZE, 1609 .is_mac = true, 1610 .template_ahash = { 1611 .init = cc_hash_init, 1612 .update = cc_hash_update, 1613 .final = cc_hash_final, 1614 .finup = cc_hash_finup, 1615 .digest = cc_hash_digest, 1616 .export = cc_hash_export, 1617 .import = cc_hash_import, 1618 .setkey = cc_hash_setkey, 1619 .halg = { 1620 .digestsize = SHA224_DIGEST_SIZE, 1621 .statesize = CC_STATE_SIZE(SHA224_DIGEST_SIZE), 1622 }, 1623 }, 1624 .hash_mode = DRV_HASH_SHA224, 1625 .hw_mode = DRV_HASH_HW_SHA256, 1626 .inter_digestsize = SHA256_DIGEST_SIZE, 1627 .min_hw_rev = CC_HW_REV_630, 1628 }, 1629 { 1630 .name = "sha384", 1631 .driver_name = "sha384-ccree", 1632 .mac_name = "hmac(sha384)", 1633 .mac_driver_name = "hmac-sha384-ccree", 1634 .blocksize = SHA384_BLOCK_SIZE, 1635 .is_mac = true, 1636 .template_ahash = { 1637 .init = cc_hash_init, 1638 .update = cc_hash_update, 1639 .final = cc_hash_final, 1640 .finup = cc_hash_finup, 1641 .digest = cc_hash_digest, 1642 .export = cc_hash_export, 1643 .import = cc_hash_import, 1644 .setkey = cc_hash_setkey, 1645 .halg = { 1646 .digestsize = SHA384_DIGEST_SIZE, 1647 .statesize = CC_STATE_SIZE(SHA384_DIGEST_SIZE), 1648 }, 1649 }, 1650 .hash_mode = DRV_HASH_SHA384, 1651 .hw_mode = DRV_HASH_HW_SHA512, 1652 .inter_digestsize = SHA512_DIGEST_SIZE, 1653 .min_hw_rev = CC_HW_REV_712, 1654 }, 1655 { 1656 .name = "sha512", 1657 .driver_name = "sha512-ccree", 1658 .mac_name = "hmac(sha512)", 1659 .mac_driver_name = "hmac-sha512-ccree", 1660 .blocksize = SHA512_BLOCK_SIZE, 1661 .is_mac = true, 1662 .template_ahash = { 1663 .init = cc_hash_init, 1664 .update = cc_hash_update, 1665 .final = cc_hash_final, 1666 .finup = cc_hash_finup, 1667 .digest = cc_hash_digest, 1668 .export = cc_hash_export, 1669 .import = cc_hash_import, 1670 .setkey = cc_hash_setkey, 1671 .halg = { 1672 .digestsize = SHA512_DIGEST_SIZE, 1673 .statesize = CC_STATE_SIZE(SHA512_DIGEST_SIZE), 1674 }, 1675 }, 1676 .hash_mode = DRV_HASH_SHA512, 1677 .hw_mode = DRV_HASH_HW_SHA512, 1678 .inter_digestsize = SHA512_DIGEST_SIZE, 1679 .min_hw_rev = CC_HW_REV_712, 1680 }, 1681 { 1682 .name = "md5", 1683 .driver_name = "md5-ccree", 1684 .mac_name = "hmac(md5)", 1685 .mac_driver_name = "hmac-md5-ccree", 1686 .blocksize = MD5_HMAC_BLOCK_SIZE, 1687 .is_mac = true, 1688 .template_ahash = { 1689 .init = cc_hash_init, 1690 .update = cc_hash_update, 1691 .final = cc_hash_final, 1692 .finup = cc_hash_finup, 1693 .digest = cc_hash_digest, 1694 .export = cc_hash_export, 1695 .import = cc_hash_import, 1696 .setkey = cc_hash_setkey, 1697 .halg = { 1698 .digestsize = MD5_DIGEST_SIZE, 1699 .statesize = CC_STATE_SIZE(MD5_DIGEST_SIZE), 1700 }, 1701 }, 1702 .hash_mode = DRV_HASH_MD5, 1703 .hw_mode = DRV_HASH_HW_MD5, 1704 .inter_digestsize = MD5_DIGEST_SIZE, 1705 .min_hw_rev = CC_HW_REV_630, 1706 }, 1707 { 1708 .name = "sm3", 1709 .driver_name = "sm3-ccree", 1710 .blocksize = SM3_BLOCK_SIZE, 1711 .is_mac = false, 1712 .template_ahash = { 1713 .init = cc_hash_init, 1714 .update = cc_hash_update, 1715 .final = cc_hash_final, 1716 .finup = cc_hash_finup, 1717 .digest = cc_hash_digest, 1718 .export = cc_hash_export, 1719 .import = cc_hash_import, 1720 .setkey = cc_hash_setkey, 1721 .halg = { 1722 .digestsize = SM3_DIGEST_SIZE, 1723 .statesize = CC_STATE_SIZE(SM3_DIGEST_SIZE), 1724 }, 1725 }, 1726 .hash_mode = DRV_HASH_SM3, 1727 .hw_mode = DRV_HASH_HW_SM3, 1728 .inter_digestsize = SM3_DIGEST_SIZE, > 1729 .min_hw_rev = CC_HW_REV_713, 1730 }, 1731 { 1732 .mac_name = "xcbc(aes)", 1733 .mac_driver_name = "xcbc-aes-ccree", 1734 .blocksize = AES_BLOCK_SIZE, 1735 .is_mac = true, 1736 .template_ahash = { 1737 .init = cc_hash_init, 1738 .update = cc_mac_update, 1739 .final = cc_mac_final, 1740 .finup = cc_mac_finup, 1741 .digest = cc_mac_digest, 1742 .setkey = cc_xcbc_setkey, 1743 .export = cc_hash_export, 1744 .import = cc_hash_import, 1745 .halg = { 1746 .digestsize = AES_BLOCK_SIZE, 1747 .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), 1748 }, 1749 }, 1750 .hash_mode = DRV_HASH_NULL, 1751 .hw_mode = DRV_CIPHER_XCBC_MAC, 1752 .inter_digestsize = AES_BLOCK_SIZE, 1753 .min_hw_rev = CC_HW_REV_630, 1754 }, 1755 { 1756 .mac_name = "cmac(aes)", 1757 .mac_driver_name = "cmac-aes-ccree", 1758 .blocksize = AES_BLOCK_SIZE, 1759 .is_mac = true, 1760 .template_ahash = { 1761 .init = cc_hash_init, 1762 .update = cc_mac_update, 1763 .final = cc_mac_final, 1764 .finup = cc_mac_finup, 1765 .digest = cc_mac_digest, 1766 .setkey = cc_cmac_setkey, 1767 .export = cc_hash_export, 1768 .import = cc_hash_import, 1769 .halg = { 1770 .digestsize = AES_BLOCK_SIZE, 1771 .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), 1772 }, 1773 }, 1774 .hash_mode = DRV_HASH_NULL, 1775 .hw_mode = DRV_CIPHER_CMAC, 1776 .inter_digestsize = AES_BLOCK_SIZE, 1777 .min_hw_rev = CC_HW_REV_630, 1778 }, 1779 }; 1780 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index a8c4ce0..1588cd4 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -751,6 +751,7 @@ config CRYPTO_DEV_CCREE select CRYPTO_ECB select CRYPTO_CTR select CRYPTO_XTS + select CRYPTO_SM3 help Say 'Y' to enable a driver for the REE interface of the Arm TrustZone CryptoCell family of processors. Currently the diff --git a/drivers/crypto/ccree/cc_crypto_ctx.h b/drivers/crypto/ccree/cc_crypto_ctx.h index e032544..c8dac27 100644 --- a/drivers/crypto/ccree/cc_crypto_ctx.h +++ b/drivers/crypto/ccree/cc_crypto_ctx.h @@ -115,7 +115,8 @@ enum drv_hash_mode { DRV_HASH_CBC_MAC = 6, DRV_HASH_XCBC_MAC = 7, DRV_HASH_CMAC = 8, - DRV_HASH_MODE_NUM = 9, + DRV_HASH_SM3 = 9, + DRV_HASH_MODE_NUM = 10, DRV_HASH_RESERVE32B = S32_MAX }; @@ -127,6 +128,7 @@ enum drv_hash_hw_mode { DRV_HASH_HW_SHA512 = 4, DRV_HASH_HW_SHA384 = 12, DRV_HASH_HW_GHASH = 6, + DRV_HASH_HW_SM3 = 14, DRV_HASH_HW_RESERVE32B = S32_MAX }; diff --git a/drivers/crypto/ccree/cc_hash.c b/drivers/crypto/ccree/cc_hash.c index adcd9df..c80c9ae 100644 --- a/drivers/crypto/ccree/cc_hash.c +++ b/drivers/crypto/ccree/cc_hash.c @@ -6,6 +6,7 @@ #include <crypto/algapi.h> #include <crypto/hash.h> #include <crypto/md5.h> +#include <crypto/sm3.h> #include <crypto/internal/hash.h> #include "cc_driver.h" @@ -16,6 +17,7 @@ #define CC_MAX_HASH_SEQ_LEN 12 #define CC_MAX_OPAD_KEYS_SIZE CC_MAX_HASH_BLCK_SIZE +#define CC_SM3_HASH_LEN_SIZE 8 struct cc_hash_handle { cc_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/ @@ -43,6 +45,9 @@ static u64 sha384_init[] = { static u64 sha512_init[] = { SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4, SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 }; +static const u32 sm3_init[] = { + SM3_IVH, SM3_IVG, SM3_IVF, SM3_IVE, + SM3_IVD, SM3_IVC, SM3_IVB, SM3_IVA }; static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[], unsigned int *seq_size); @@ -1074,7 +1079,10 @@ static int cc_get_hash_len(struct crypto_tfm *tfm) { struct cc_hash_ctx *ctx = crypto_tfm_ctx(tfm); - return cc_get_default_hash_len(ctx->drvdata); + if (ctx->hash_mode == DRV_HASH_SM3) + return CC_SM3_HASH_LEN_SIZE; + else + return cc_get_default_hash_len(ctx->drvdata); } static int cc_cra_init(struct crypto_tfm *tfm) @@ -1523,6 +1531,7 @@ struct cc_hash_template { char mac_name[CRYPTO_MAX_ALG_NAME]; char mac_driver_name[CRYPTO_MAX_ALG_NAME]; unsigned int blocksize; + bool is_mac; bool synchronize; struct ahash_alg template_ahash; int hash_mode; @@ -1544,6 +1553,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(sha1)", .mac_driver_name = "hmac-sha1-ccree", .blocksize = SHA1_BLOCK_SIZE, + .is_mac = true, .synchronize = false, .template_ahash = { .init = cc_hash_init, @@ -1570,6 +1580,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(sha256)", .mac_driver_name = "hmac-sha256-ccree", .blocksize = SHA256_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_hash_update, @@ -1595,6 +1606,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(sha224)", .mac_driver_name = "hmac-sha224-ccree", .blocksize = SHA224_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_hash_update, @@ -1620,6 +1632,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(sha384)", .mac_driver_name = "hmac-sha384-ccree", .blocksize = SHA384_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_hash_update, @@ -1645,6 +1658,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(sha512)", .mac_driver_name = "hmac-sha512-ccree", .blocksize = SHA512_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_hash_update, @@ -1670,6 +1684,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "hmac(md5)", .mac_driver_name = "hmac-md5-ccree", .blocksize = MD5_HMAC_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_hash_update, @@ -1690,9 +1705,34 @@ static struct cc_hash_template driver_hash[] = { .min_hw_rev = CC_HW_REV_630, }, { + .name = "sm3", + .driver_name = "sm3-ccree", + .blocksize = SM3_BLOCK_SIZE, + .is_mac = false, + .template_ahash = { + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, + .halg = { + .digestsize = SM3_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SM3_DIGEST_SIZE), + }, + }, + .hash_mode = DRV_HASH_SM3, + .hw_mode = DRV_HASH_HW_SM3, + .inter_digestsize = SM3_DIGEST_SIZE, + .min_hw_rev = CC_HW_REV_713, + }, + { .mac_name = "xcbc(aes)", .mac_driver_name = "xcbc-aes-ccree", .blocksize = AES_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_mac_update, @@ -1716,6 +1756,7 @@ static struct cc_hash_template driver_hash[] = { .mac_name = "cmac(aes)", .mac_driver_name = "cmac-aes-ccree", .blocksize = AES_BLOCK_SIZE, + .is_mac = true, .template_ahash = { .init = cc_hash_init, .update = cc_mac_update, @@ -1788,6 +1829,7 @@ int cc_init_hash_sram(struct cc_drvdata *drvdata) unsigned int larval_seq_len = 0; struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; bool large_sha_supported = (drvdata->hw_rev >= CC_HW_REV_712); + bool sm3_supported = (drvdata->hw_rev >= CC_HW_REV_713); int rc = 0; /* Copy-to-sram digest-len */ @@ -1853,6 +1895,17 @@ int cc_init_hash_sram(struct cc_drvdata *drvdata) sram_buff_ofs += sizeof(sha256_init); larval_seq_len = 0; + if (sm3_supported) { + cc_set_sram_desc(sm3_init, sram_buff_ofs, + ARRAY_SIZE(sm3_init), larval_seq, + &larval_seq_len); + rc = send_request_init(drvdata, larval_seq, larval_seq_len); + if (rc) + goto init_digest_const_err; + sram_buff_ofs += sizeof(sm3_init); + larval_seq_len = 0; + } + if (large_sha_supported) { cc_set_sram_desc((u32 *)sha384_init, sram_buff_ofs, (ARRAY_SIZE(sha384_init) * 2), larval_seq, @@ -1919,6 +1972,9 @@ int cc_hash_alloc(struct cc_drvdata *drvdata) sizeof(sha224_init) + sizeof(sha256_init); + if (drvdata->hw_rev >= CC_HW_REV_713) + sram_size_to_alloc += sizeof(sm3_init); + if (drvdata->hw_rev >= CC_HW_REV_712) sram_size_to_alloc += sizeof(digest_len_sha512_init) + sizeof(sha384_init) + sizeof(sha512_init); @@ -1948,27 +2004,28 @@ int cc_hash_alloc(struct cc_drvdata *drvdata) /* We either support both HASH and MAC or none */ if (driver_hash[alg].min_hw_rev > drvdata->hw_rev) continue; - - /* register hmac version */ - t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true); - if (IS_ERR(t_alg)) { - rc = PTR_ERR(t_alg); - dev_err(dev, "%s alg allocation failed\n", - driver_hash[alg].driver_name); - goto fail; - } - t_alg->drvdata = drvdata; - - rc = crypto_register_ahash(&t_alg->ahash_alg); - if (rc) { - dev_err(dev, "%s alg registration failed\n", - driver_hash[alg].driver_name); - kfree(t_alg); - goto fail; - } else { - list_add_tail(&t_alg->entry, &hash_handle->hash_list); + if (driver_hash[alg].is_mac) { + /* register hmac version */ + t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true); + if (IS_ERR(t_alg)) { + rc = PTR_ERR(t_alg); + dev_err(dev, "%s alg allocation failed\n", + driver_hash[alg].driver_name); + goto fail; + } + t_alg->drvdata = drvdata; + + rc = crypto_register_ahash(&t_alg->ahash_alg); + if (rc) { + dev_err(dev, "%s alg registration failed\n", + driver_hash[alg].driver_name); + kfree(t_alg); + goto fail; + } else { + list_add_tail(&t_alg->entry, + &hash_handle->hash_list); + } } - if (hw_mode == DRV_CIPHER_XCBC_MAC || hw_mode == DRV_CIPHER_CMAC) continue; @@ -2170,6 +2227,8 @@ static const void *cc_larval_digest(struct device *dev, u32 mode) return sha384_init; case DRV_HASH_SHA512: return sha512_init; + case DRV_HASH_SM3: + return sm3_init; default: dev_err(dev, "Invalid hash mode (%d)\n", mode); return md5_init; @@ -2190,6 +2249,8 @@ cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) struct cc_drvdata *_drvdata = (struct cc_drvdata *)drvdata; struct cc_hash_handle *hash_handle = _drvdata->hash_handle; struct device *dev = drvdata_to_dev(_drvdata); + bool sm3_supported = (_drvdata->hw_rev >= CC_HW_REV_713); + cc_sram_addr_t addr; switch (mode) { case DRV_HASH_NULL: @@ -2208,19 +2269,31 @@ cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) sizeof(md5_init) + sizeof(sha1_init) + sizeof(sha224_init)); - case DRV_HASH_SHA384: + case DRV_HASH_SM3: return (hash_handle->larval_digest_sram_addr + sizeof(md5_init) + sizeof(sha1_init) + sizeof(sha224_init) + sizeof(sha256_init)); + case DRV_HASH_SHA384: + addr = (hash_handle->larval_digest_sram_addr + + sizeof(md5_init) + + sizeof(sha1_init) + + sizeof(sha224_init) + + sizeof(sha256_init)); + if (sm3_supported) + addr += sizeof(sm3_init); + return addr; case DRV_HASH_SHA512: - return (hash_handle->larval_digest_sram_addr + + addr = (hash_handle->larval_digest_sram_addr + sizeof(md5_init) + sizeof(sha1_init) + sizeof(sha224_init) + sizeof(sha256_init) + sizeof(sha384_init)); + if (sm3_supported) + addr += sizeof(sm3_init); + return addr; default: dev_err(dev, "Invalid hash mode (%d)\n", mode); } diff --git a/drivers/crypto/ccree/cc_hw_queue_defs.h b/drivers/crypto/ccree/cc_hw_queue_defs.h index b367b67..e1783ea 100644 --- a/drivers/crypto/ccree/cc_hw_queue_defs.h +++ b/drivers/crypto/ccree/cc_hw_queue_defs.h @@ -42,6 +42,7 @@ #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) +#define WORD4_AES_XOR_CRYPTO_KEY CC_GENMASK(4, AES_XOR_CRYPTO_KEY) #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) @@ -394,6 +395,16 @@ static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) } /* + * Set aes xor crypto key, this in some secenrios select SM3 engine + * + * @pdesc: pointer HW descriptor struct + */ +static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1); +} + +/* * Set the DOUT field of a HW descriptors to SRAM mode * Note: No need to check SRAM alignment since host requests do not use SRAM and * adaptor will enforce alignment check. @@ -466,6 +477,8 @@ static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, enum drv_hash_mode hash_mode) { set_cipher_mode(pdesc, cipher_mode); + if (hash_mode == DRV_HASH_SM3) + set_aes_xor_crypto_key(pdesc); } /*
Add support for SM3 cipher in CryptoCell 713. Signed-off-by: Yael Chemla <yael.chemla@foss.arm.com> --- drivers/crypto/Kconfig | 1 + drivers/crypto/ccree/cc_crypto_ctx.h | 4 +- drivers/crypto/ccree/cc_hash.c | 119 ++++++++++++++++++++++++++------ drivers/crypto/ccree/cc_hw_queue_defs.h | 13 ++++ 4 files changed, 113 insertions(+), 24 deletions(-)