| Message ID | 20181023233620.10159-1-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE. | expand |
On Tue, 23 Oct 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > RANGE makes it longer, but clear. IS_GEN_RANGE() was the first proposal, but in review this was changed to IS_GEN() following IS_REVID() and IS_<platform>_REVID(). IMO unnecessary change. BR, Jani. > > Diff generated with: > > sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > drivers/gpu/drm/i915/intel_bios.c | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ > 9 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 5b37d5f8e132..3deab30388f2 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) > if (IS_BROXTON(dev_priv)) { > seq_printf(m, "DC3 -> DC5 count: %d\n", > I915_READ(BXT_CSR_DC3_DC5_COUNT)); > - } else if (IS_GEN(dev_priv, 9, 11)) { > + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) { > seq_printf(m, "DC3 -> DC5 count: %d\n", > I915_READ(SKL_CSR_DC3_DC5_COUNT)); > seq_printf(m, "DC5 -> DC6 count: %d\n", > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 3017ef037fed..f766bb1e873b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv) > * > * Use GEN_FOREVER for unbound start and or end. > */ > -#define IS_GEN(dev_priv, s, e) \ > +#define IS_GEN_RANGE(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > /* > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 664b96bb65a3..0888b6e6080f 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, > * be read back from automatically triggered reports, as part of the > * RPT_ID field. > */ > - if (IS_GEN(dev_priv, 9, 11)) { > + if (IS_GEN_RANGE(dev_priv, 9, 11)) { > I915_WRITE(GEN8_OA_DEBUG, > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); > @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); > } > - } else if (IS_GEN(dev_priv, 10, 11)) { > + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) { > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > gen7_is_valid_b_counter_addr; > dev_priv->perf.oa.ops.is_valid_mux_reg = > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > index 1faa494e2bc9..43cf0b026143 100644 > --- a/drivers/gpu/drm/i915/intel_bios.c > +++ b/drivers/gpu/drm/i915/intel_bios.c > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) > * Only parse SDVO mappings on gens that could have SDVO. This isn't > * accurate and doesn't have to be, as long as it's not too strict. > */ > - if (!IS_GEN(dev_priv, 3, 7)) { > + if (!IS_GEN_RANGE(dev_priv, 3, 7)) { > DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); > return; > } > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 8bfab22068a3..65f6c9bc10cf 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, > &engine->execlists; > u64 addr; > > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) > + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7)) > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); > drm_printf(m, "\tRING_START: 0x%08x\n", > I915_READ(RING_START(engine->mmio_base))); > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index e3cfc3c176e7..c90954cdfb15 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > * having a Y offset that isn't divisible by 4 causes FIFO underrun > * and screen flicker. > */ > - if (IS_GEN(dev_priv, 9, 10) && > + if (IS_GEN_RANGE(dev_priv, 9, 10) && > (fbc->state_cache.plane.adjusted_y & 3)) { > fbc->no_fbc_reason = "plane Y offset is misaligned"; > return false; > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > index e26d05a46451..41921a843d42 100644 > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > return ENGINE_WAIT_KICK; > } > > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > switch (semaphore_passed(engine)) { > default: > return ENGINE_DEAD; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index b8a7a014d46d..608e5c65b655 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > POSTING_READ(mmio); > > /* Flush the TLB for this page */ > - if (IS_GEN(dev_priv, 6, 7)) { > + if (IS_GEN_RANGE(dev_priv, 6, 7)) { > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > /* ring should be idle before issuing a sync flush*/ > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > intel_whitelist_workarounds_apply(engine); > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > - if (IS_GEN(dev_priv, 4, 6)) > + if (IS_GEN_RANGE(dev_priv, 4, 6)) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > /* We need to disable the AsyncFlip performance optimisations in order > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > * > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > */ > - if (IS_GEN(dev_priv, 6, 7)) > + if (IS_GEN_RANGE(dev_priv, 6, 7)) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > /* Required for the hardware to program scanline values for waiting */ > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > } > > - if (IS_GEN(dev_priv, 6, 7)) > + if (IS_GEN_RANGE(dev_priv, 6, 7)) > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > if (INTEL_GEN(dev_priv) >= 6) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 9289515108c3..631b4165fe00 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > dev_priv->uncore.pmic_bus_access_nb.notifier_call = > i915_pmic_bus_access_notifier; > > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > } else if (IS_GEN5(dev_priv)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > - } else if (IS_GEN(dev_priv, 6, 7)) { > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); > > if (IS_VALLEYVIEW(dev_priv)) { > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > } > - } else if (IS_GEN(dev_priv, 9, 10)) { > + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) { > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, > } else if (INTEL_GEN(dev_priv) >= 6) { > fw_domains = __gen6_reg_read_fw_domains(offset); > } else { > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); > fw_domains = 0; > } > > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > fw_domains = __fwtable_reg_write_fw_domains(offset); > } else if (IS_GEN8(dev_priv)) { > fw_domains = __gen8_reg_write_fw_domains(offset); > - } else if (IS_GEN(dev_priv, 6, 7)) { > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { > fw_domains = FORCEWAKE_RENDER; > } else { > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); > fw_domains = 0; > }
On Mon, Oct 29, 2018 at 12:19:37PM +0200, Jani Nikula wrote: > On Tue, 23 Oct 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > RANGE makes it longer, but clear. > > IS_GEN_RANGE() was the first proposal, but in review this was changed to > IS_GEN() following IS_REVID() and IS_<platform>_REVID(). > > IMO unnecessary change. consider this one dropped then. other 2 patches from this series got pushed. Thanks, Rodrigo. > > BR, > Jani. > > > > > Diff generated with: > > > > sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > > drivers/gpu/drm/i915/intel_bios.c | 2 +- > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- > > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ > > 9 files changed, 18 insertions(+), 18 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index 5b37d5f8e132..3deab30388f2 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) > > if (IS_BROXTON(dev_priv)) { > > seq_printf(m, "DC3 -> DC5 count: %d\n", > > I915_READ(BXT_CSR_DC3_DC5_COUNT)); > > - } else if (IS_GEN(dev_priv, 9, 11)) { > > + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) { > > seq_printf(m, "DC3 -> DC5 count: %d\n", > > I915_READ(SKL_CSR_DC3_DC5_COUNT)); > > seq_printf(m, "DC5 -> DC6 count: %d\n", > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 3017ef037fed..f766bb1e873b 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv) > > * > > * Use GEN_FOREVER for unbound start and or end. > > */ > > -#define IS_GEN(dev_priv, s, e) \ > > +#define IS_GEN_RANGE(dev_priv, s, e) \ > > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > > > /* > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > index 664b96bb65a3..0888b6e6080f 100644 > > --- a/drivers/gpu/drm/i915/i915_perf.c > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, > > * be read back from automatically triggered reports, as part of the > > * RPT_ID field. > > */ > > - if (IS_GEN(dev_priv, 9, 11)) { > > + if (IS_GEN_RANGE(dev_priv, 9, 11)) { > > I915_WRITE(GEN8_OA_DEBUG, > > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | > > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); > > @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); > > } > > - } else if (IS_GEN(dev_priv, 10, 11)) { > > + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) { > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > gen7_is_valid_b_counter_addr; > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > > index 1faa494e2bc9..43cf0b026143 100644 > > --- a/drivers/gpu/drm/i915/intel_bios.c > > +++ b/drivers/gpu/drm/i915/intel_bios.c > > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) > > * Only parse SDVO mappings on gens that could have SDVO. This isn't > > * accurate and doesn't have to be, as long as it's not too strict. > > */ > > - if (!IS_GEN(dev_priv, 3, 7)) { > > + if (!IS_GEN_RANGE(dev_priv, 3, 7)) { > > DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); > > return; > > } > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > index 8bfab22068a3..65f6c9bc10cf 100644 > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, > > &engine->execlists; > > u64 addr; > > > > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) > > + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7)) > > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); > > drm_printf(m, "\tRING_START: 0x%08x\n", > > I915_READ(RING_START(engine->mmio_base))); > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > > index e3cfc3c176e7..c90954cdfb15 100644 > > --- a/drivers/gpu/drm/i915/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/intel_fbc.c > > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > > * having a Y offset that isn't divisible by 4 causes FIFO underrun > > * and screen flicker. > > */ > > - if (IS_GEN(dev_priv, 9, 10) && > > + if (IS_GEN_RANGE(dev_priv, 9, 10) && > > (fbc->state_cache.plane.adjusted_y & 3)) { > > fbc->no_fbc_reason = "plane Y offset is misaligned"; > > return false; > > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > > index e26d05a46451..41921a843d42 100644 > > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > > return ENGINE_WAIT_KICK; > > } > > > > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > switch (semaphore_passed(engine)) { > > default: > > return ENGINE_DEAD; > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index b8a7a014d46d..608e5c65b655 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > > POSTING_READ(mmio); > > > > /* Flush the TLB for this page */ > > - if (IS_GEN(dev_priv, 6, 7)) { > > + if (IS_GEN_RANGE(dev_priv, 6, 7)) { > > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > > > /* ring should be idle before issuing a sync flush*/ > > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > intel_whitelist_workarounds_apply(engine); > > > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > > - if (IS_GEN(dev_priv, 4, 6)) > > + if (IS_GEN_RANGE(dev_priv, 4, 6)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > > > /* We need to disable the AsyncFlip performance optimisations in order > > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > * > > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > > */ > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (IS_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > > > /* Required for the hardware to program scanline values for waiting */ > > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > > } > > > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (IS_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > > > if (INTEL_GEN(dev_priv) >= 6) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index 9289515108c3..631b4165fe00 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > dev_priv->uncore.pmic_bus_access_nb.notifier_call = > > i915_pmic_bus_access_notifier; > > > > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > > } else if (IS_GEN5(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); > > > > if (IS_VALLEYVIEW(dev_priv)) { > > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > > } > > - } else if (IS_GEN(dev_priv, 9, 10)) { > > + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) { > > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); > > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, > > } else if (INTEL_GEN(dev_priv) >= 6) { > > fw_domains = __gen6_reg_read_fw_domains(offset); > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > > > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > > fw_domains = __fwtable_reg_write_fw_domains(offset); > > } else if (IS_GEN8(dev_priv)) { > > fw_domains = __gen8_reg_write_fw_domains(offset); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { > > fw_domains = FORCEWAKE_RENDER; > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5b37d5f8e132..3deab30388f2 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) if (IS_BROXTON(dev_priv)) { seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(BXT_CSR_DC3_DC5_COUNT)); - } else if (IS_GEN(dev_priv, 9, 11)) { + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) { seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(SKL_CSR_DC3_DC5_COUNT)); seq_printf(m, "DC5 -> DC6 count: %d\n", diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3017ef037fed..f766bb1e873b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv) * * Use GEN_FOREVER for unbound start and or end. */ -#define IS_GEN(dev_priv, s, e) \ +#define IS_GEN_RANGE(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) /* diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 664b96bb65a3..0888b6e6080f 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, * be read back from automatically triggered reports, as part of the * RPT_ID field. */ - if (IS_GEN(dev_priv, 9, 11)) { + if (IS_GEN_RANGE(dev_priv, 9, 11)) { I915_WRITE(GEN8_OA_DEBUG, _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); } - } else if (IS_GEN(dev_priv, 10, 11)) { + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 1faa494e2bc9..43cf0b026143 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) * Only parse SDVO mappings on gens that could have SDVO. This isn't * accurate and doesn't have to be, as long as it's not too strict. */ - if (!IS_GEN(dev_priv, 3, 7)) { + if (!IS_GEN_RANGE(dev_priv, 3, 7)) { DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); return; } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 8bfab22068a3..65f6c9bc10cf 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, &engine->execlists; u64 addr; - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7)) drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); drm_printf(m, "\tRING_START: 0x%08x\n", I915_READ(RING_START(engine->mmio_base))); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index e3cfc3c176e7..c90954cdfb15 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * having a Y offset that isn't divisible by 4 causes FIFO underrun * and screen flicker. */ - if (IS_GEN(dev_priv, 9, 10) && + if (IS_GEN_RANGE(dev_priv, 9, 10) && (fbc->state_cache.plane.adjusted_y & 3)) { fbc->no_fbc_reason = "plane Y offset is misaligned"; return false; diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index e26d05a46451..41921a843d42 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) return ENGINE_WAIT_KICK; } - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { switch (semaphore_passed(engine)) { default: return ENGINE_DEAD; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b8a7a014d46d..608e5c65b655 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) POSTING_READ(mmio); /* Flush the TLB for this page */ - if (IS_GEN(dev_priv, 6, 7)) { + if (IS_GEN_RANGE(dev_priv, 6, 7)) { i915_reg_t reg = RING_INSTPM(engine->mmio_base); /* ring should be idle before issuing a sync flush*/ @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) intel_whitelist_workarounds_apply(engine); /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - if (IS_GEN(dev_priv, 4, 6)) + if (IS_GEN_RANGE(dev_priv, 4, 6)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) * * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv */ - if (IS_GEN(dev_priv, 6, 7)) + if (IS_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); /* Required for the hardware to program scanline values for waiting */ @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); } - if (IS_GEN(dev_priv, 6, 7)) + if (IS_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); if (INTEL_GEN(dev_priv) >= 6) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9289515108c3..631b4165fe00 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) dev_priv->uncore.pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); } else if (IS_GEN5(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); - } else if (IS_GEN(dev_priv, 6, 7)) { + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); if (IS_VALLEYVIEW(dev_priv)) { @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); } - } else if (IS_GEN(dev_priv, 9, 10)) { + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) { ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, } else if (INTEL_GEN(dev_priv) >= 6) { fw_domains = __gen6_reg_read_fw_domains(offset); } else { - WARN_ON(!IS_GEN(dev_priv, 2, 5)); + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); fw_domains = 0; } @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, fw_domains = __fwtable_reg_write_fw_domains(offset); } else if (IS_GEN8(dev_priv)) { fw_domains = __gen8_reg_write_fw_domains(offset); - } else if (IS_GEN(dev_priv, 6, 7)) { + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { fw_domains = FORCEWAKE_RENDER; } else { - WARN_ON(!IS_GEN(dev_priv, 2, 5)); + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5)); fw_domains = 0; }
RANGE makes it longer, but clear. Diff generated with: sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_fbc.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ 9 files changed, 18 insertions(+), 18 deletions(-)