diff mbox series

drm/i915: Fix spelling mistake in intel_psr

Message ID 20181026194520.129663-1-sean@poorly.run (mailing list archive)
State New, archived
Headers show
Series drm/i915: Fix spelling mistake in intel_psr | expand

Commit Message

Sean Paul Oct. 26, 2018, 7:45 p.m. UTC
From: Sean Paul <seanpaul@chromium.org>

Noticed this while reading the comments, s/defesive/defensive/

Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/i915/intel_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Rodrigo Vivi Oct. 26, 2018, 8:07 p.m. UTC | #1
On Fri, Oct 26, 2018 at 03:45:04PM -0400, Sean Paul wrote:
> From: Sean Paul <seanpaul@chromium.org>
> 
> Noticed this while reading the comments, s/defesive/defensive/
> 
> Signed-off-by: Sean Paul <seanpaul@chromium.org>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 4bd5768731ee..562718cbb198 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -748,7 +748,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
>  	/*
>  	 * Max time for PSR to idle = Inverse of the refresh rate +
>  	 * 6 ms of exit training time + 1.5 ms of aux channel
> -	 * handshake. 50 msec is defesive enough to cover everything.
> +	 * handshake. 50 msec is defensive enough to cover everything.
>  	 */
>  	return intel_wait_for_register(dev_priv, reg, mask,
>  				       EDP_PSR_STATUS_STATE_IDLE, 50);
> -- 
> Sean Paul, Software Engineer, Google / Chromium OS
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4bd5768731ee..562718cbb198 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -748,7 +748,7 @@  int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
 	/*
 	 * Max time for PSR to idle = Inverse of the refresh rate +
 	 * 6 ms of exit training time + 1.5 ms of aux channel
-	 * handshake. 50 msec is defesive enough to cover everything.
+	 * handshake. 50 msec is defensive enough to cover everything.
 	 */
 	return intel_wait_for_register(dev_priv, reg, mask,
 				       EDP_PSR_STATUS_STATE_IDLE, 50);