[RFC,4/4] drm/i915: Expand DISPLAY_GEN macro usage to display related files.

Message ID	20181030003413.8144-4-rodrigo.vivi@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: intel-gfx@lists.freedesktop.org Date: Mon, 29 Oct 2018 17:34:13 -0700 Message-Id: <20181030003413.8144-4-rodrigo.vivi@intel.com> In-Reply-To: <20181030003413.8144-1-rodrigo.vivi@intel.com> References: <20181030003413.8144-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 4/4] drm/i915: Expand DISPLAY_GEN macro usage to display related files. Precedence: list Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	[RFC,1/4] drm/i915: Add Display Gen info. \| expand [RFC,1/4] drm/i915: Add Display Gen info. [RFC,2/4] drm/i915: Finally recognize Geminilake as Gen10 Display [RFC,3/4] drm/i915: Use Display gen9 for gen9_bc \|\| bxt [RFC,4/4] drm/i915: Expand DISPLAY_GEN macro usage to display related files.

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index ccd88da20a14..0407089c4ccd 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -733,7 +733,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv) } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; - } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { + } else if (IS_HASWELL(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 8) { dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; } else if (HAS_PCH_SPLIT(dev_priv)) { @@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, struct drm_i915_private *dev_priv = kdev_to_i915(kdev); u32 tmp; - if (!IS_GEN9(dev_priv)) + if (!IS_DISPLAY_GEN9(dev_priv)) return; i915_audio_component_get_power(kdev); diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 093f75dc0aee..d32faf7feb23 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, { if (INTEL_DISPLAY_GEN(dev_priv) >= 10) return DIV_ROUND_UP(pixel_rate, 2); - else if (IS_GEN9(dev_priv) || + else if (IS_DISPLAY_GEN9(dev_priv) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; else if (IS_CHERRYVIEW(dev_priv)) @@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) if (IS_DISPLAY_GEN10(dev_priv)) { /* Display WA #1145: glk,cnl */ min_cdclk = max(316800, min_cdclk); - } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { + } else if (IS_DISPLAY_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { /* Display WA #1144: skl,bxt */ min_cdclk = max(432000, min_cdclk); } @@ -2197,7 +2197,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * at probe time. If we probe without displays, we'll still end up using * the platform minimum CDCLK, failing audio probe. */ - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) min_cdclk = max(2 * 96000, min_cdclk); /* @@ -2537,12 +2537,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) if (INTEL_DISPLAY_GEN(dev_priv) >= 10) return 2 * max_cdclk_freq; - else if (IS_GEN9(dev_priv) || + else if (IS_DISPLAY_GEN9(dev_priv) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) return max_cdclk_freq*95/100; - else if (INTEL_GEN(dev_priv) < 4) + else if (INTEL_DISPLAY_GEN(dev_priv) < 4) return 2*max_cdclk_freq*90/100; else return max_cdclk_freq*90/100; @@ -2806,9 +2806,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.get_cdclk = hsw_get_cdclk; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->display.get_cdclk = vlv_get_cdclk; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + else if (IS_DISPLAY_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_GEN5(dev_priv)) + else if (IS_DISPLAY_GEN5(dev_priv)) dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; else if (IS_GM45(dev_priv)) dev_priv->display.get_cdclk = gm45_get_cdclk; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 70aaf915245c..18eeafa5e27f 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -146,7 +146,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state) * FIXME if there's a gamma LUT after the CSC, we should * do the range compression using the gamma LUT instead. */ - if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) limited_color_range = intel_crtc_state->limited_color_range; if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || @@ -229,7 +229,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); - if (INTEL_GEN(dev_priv) > 6) { + if (INTEL_DISPLAY_GEN(dev_priv) > 6) { uint16_t postoff = 0; if (limited_color_range) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 68f2fb89ece3..c331103476f4 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -156,7 +156,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; u32 adpa; - if (INTEL_GEN(dev_priv) >= 5) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) adpa = ADPA_HOTPLUG_BITS; else adpa = 0; @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, * DAC limit supposedly 355 MHz. */ max_clock = 270000; - else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) + else if (IS_DISPLAY_GEN3(dev_priv) || IS_DISPLAY_GEN4(dev_priv)) max_clock = 400000; else max_clock = 350000; @@ -833,7 +833,7 @@ intel_crt_detect(struct drm_connector *connector, if (ret > 0) { if (intel_crt_detect_ddc(connector)) status = connector_status_connected; - else if (INTEL_GEN(dev_priv) < 4) + else if (INTEL_DISPLAY_GEN(dev_priv) < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); else if (i915_modparams.load_detect_test) @@ -883,7 +883,7 @@ void intel_crt_reset(struct drm_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); - if (INTEL_GEN(dev_priv) >= 5) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) { u32 adpa; adpa = I915_READ(crt->adpa_reg); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e40a8c97d34b..fedd9503682f 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1369,7 +1369,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, uint32_t cfgcr0, cfgcr1; uint32_t p0, p1, p2, dco_freq, ref_clock; - if (INTEL_GEN(dev_priv) >= 11) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) { cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); } else { @@ -1745,7 +1745,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, bxt_ddi_clock_get(encoder, pipe_config); else if (IS_GEN9_BC(dev_priv)) skl_ddi_clock_get(encoder, pipe_config); - else if (INTEL_GEN(dev_priv) <= 8) + else if (INTEL_DISPLAY_GEN(dev_priv) <= 8) hsw_ddi_clock_get(encoder, pipe_config); } @@ -2863,7 +2863,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, I915_WRITE(DPLL_CTRL2, val); - } else if (INTEL_GEN(dev_priv) < 9) { + } else if (INTEL_DISPLAY_GEN(dev_priv) < 9) { I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); } @@ -2884,7 +2884,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_GEN9_BC(dev_priv)) { I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); - } else if (INTEL_GEN(dev_priv) < 9) { + } else if (INTEL_DISPLAY_GEN(dev_priv) < 9) { I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } } @@ -2931,7 +2931,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, if (!is_mst) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) + if (port != PORT_A || INTEL_DISPLAY_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); icl_enable_phy_clock_gating(dig_port); @@ -3163,7 +3163,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = encoder->port; - if (port == PORT_A && INTEL_GEN(dev_priv) < 9) + if (port == PORT_A && INTEL_DISPLAY_GEN(dev_priv) < 9) intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(crtc_state, conn_state); @@ -3756,7 +3756,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) enum port port = intel_dport->base.port; int max_lanes = 4; - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) return max_lanes; if (port == PORT_A || port == PORT_E) { @@ -3842,7 +3842,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) for_each_pipe(dev_priv, pipe) intel_encoder->crtc_mask |= BIT(pipe); - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_PORT_REVERSAL; else diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 74bd4add27f8..ac02ae2a1e75 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1038,7 +1038,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; i915_reg_t reg = PIPECONF(cpu_transcoder); @@ -1125,7 +1125,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, u32 val; /* ILK FDI PLL is always enabled */ - if (IS_GEN5(dev_priv)) + if (IS_DISPLAY_GEN5(dev_priv)) return; /* On Haswell, DDI ports are responsible for the FDI PLL setup */ @@ -1495,7 +1495,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc, POSTING_READ(reg); udelay(150); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { I915_WRITE(DPLL_MD(crtc->pipe), crtc_state->dpll_hw_state.dpll_md); } else { @@ -1983,12 +1983,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) return 256 * 1024; else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return 128 * 1024; - else if (INTEL_GEN(dev_priv) >= 4) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) return 4 * 1024; else return 0; @@ -2007,7 +2007,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, case DRM_FORMAT_MOD_LINEAR: return intel_linear_alignment(dev_priv); case I915_FORMAT_MOD_X_TILED: - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) return 256 * 1024; return 0; case I915_FORMAT_MOD_Y_TILED_CCS: @@ -2026,7 +2026,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) struct intel_plane *plane = to_intel_plane(plane_state->base.plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - return INTEL_GEN(dev_priv) < 4 || plane->has_fbc; + return INTEL_DISPLAY_GEN(dev_priv) < 4 || plane->has_fbc; } struct i915_vma * @@ -2102,7 +2102,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, * mode that matches the user configuration. */ ret = i915_vma_pin_fence(vma); - if (ret != 0 && INTEL_GEN(dev_priv) < 4) { + if (ret != 0 && INTEL_DISPLAY_GEN(dev_priv) < 4) { i915_gem_object_unpin_from_display_plane(vma); vma = ERR_PTR(ret); goto err; @@ -3160,12 +3160,12 @@ i9xx_plane_max_stride(struct intel_plane *plane, if (!HAS_GMCH_DISPLAY(dev_priv)) { return 32*1024; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { if (modifier == I915_FORMAT_MOD_X_TILED) return 16*1024; else return 32*1024; - } else if (INTEL_GEN(dev_priv) >= 3) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 3) { if (modifier == I915_FORMAT_MOD_X_TILED) return 8*1024; else @@ -3190,14 +3190,14 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; - if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || - IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (IS_G4X(dev_priv) || IS_DISPLAY_GEN5(dev_priv) || + IS_DISPLAY_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; - if (INTEL_GEN(dev_priv) < 5) + if (INTEL_DISPLAY_GEN(dev_priv) < 5) dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); switch (fb->format->format) { @@ -3227,7 +3227,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, return 0; } - if (INTEL_GEN(dev_priv) >= 4 && + if (INTEL_DISPLAY_GEN(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISPPLANE_TILED; @@ -3260,7 +3260,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) offset = intel_plane_compute_aligned_offset(&src_x, &src_y, plane_state, 0); else @@ -3336,14 +3336,14 @@ static void i9xx_update_plane(struct intel_plane *plane, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) dspaddr_offset = plane_state->color_plane[0].offset; else dspaddr_offset = linear_offset; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - if (INTEL_GEN(dev_priv) < 4) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4) { /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ @@ -3367,7 +3367,7 @@ static void i9xx_update_plane(struct intel_plane *plane, intel_plane_ggtt_offset(plane_state) + dspaddr_offset); I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { I915_WRITE_FW(DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); @@ -3393,7 +3393,7 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); I915_WRITE_FW(DSPCNTR(i9xx_plane), 0); - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) I915_WRITE_FW(DSPSURF(i9xx_plane), 0); else I915_WRITE_FW(DSPADDR(i9xx_plane), 0); @@ -3424,7 +3424,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, ret = val & DISPLAY_PLANE_ENABLE; - if (INTEL_GEN(dev_priv) >= 5) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) *pipe = plane->pipe; else *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> @@ -3652,7 +3652,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= skl_plane_ctl_tiling(fb->modifier); plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); - if (INTEL_GEN(dev_priv) >= 10) + if (INTEL_DISPLAY_GEN(dev_priv) >= 10) plane_ctl |= cnl_plane_ctl_flip(rotation & DRM_MODE_REFLECT_MASK); @@ -3672,7 +3672,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, const struct drm_framebuffer *fb = plane_state->base.fb; u32 plane_color_ctl = 0; - if (INTEL_GEN(dev_priv) < 11) { + if (INTEL_DISPLAY_GEN(dev_priv) < 11) { plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; } @@ -3734,7 +3734,7 @@ __intel_display_resume(struct drm_device *dev, static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) { return intel_has_gpu_reset(dev_priv) && - INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); + INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); } void intel_prepare_reset(struct drm_i915_private *dev_priv) @@ -3870,7 +3870,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta (new_crtc_state->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { skl_detach_scalers(new_crtc_state); if (new_crtc_state->pch_pfit.enabled) @@ -4107,7 +4107,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp = I915_READ(reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - if (IS_GEN6(dev_priv)) { + if (IS_DISPLAY_GEN6(dev_priv)) { temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; @@ -4835,7 +4835,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, * Once NV12 is enabled, handle it here while allocating scaler * for NV12. */ - if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 && crtc_state->base.enable && need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); return -EINVAL; @@ -4874,10 +4874,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, /* range checks */ if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || - (IS_GEN11(dev_priv) && + (IS_DISPLAY_GEN11(dev_priv) && (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || - (!IS_GEN11(dev_priv) && + (!IS_DISPLAY_GEN11(dev_priv) && (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " @@ -5242,7 +5242,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) || + if ((IS_DISPLAY_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) || IS_CANNONLAKE(dev_priv)) return true; @@ -5670,7 +5670,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (pipe_config->shared_dpll) intel_enable_shared_dpll(pipe_config); - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) icl_map_plls_to_ports(crtc, pipe_config, old_state); intel_encoders_pre_enable(crtc, pipe_config, old_state); @@ -5709,7 +5709,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (psl_clkgate_wa) glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) skylake_pfit_enable(pipe_config); else ironlake_pfit_enable(pipe_config); @@ -5724,7 +5724,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, * Display WA #1153: enable hardware to bypass the alpha math * and rounding for per-pixel values 00 and 0xff */ - if (INTEL_GEN(dev_priv) >= 11) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) { pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) I915_WRITE_FW(PIPE_CHICKEN(pipe), @@ -5738,7 +5738,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (dev_priv->display.initial_watermarks != NULL) dev_priv->display.initial_watermarks(old_intel_state, pipe_config); - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) icl_pipe_mbus_enable(intel_crtc); /* XXX: Do the pipe assertions at the right place for BXT DSI. */ @@ -5867,14 +5867,14 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(old_crtc_state); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(old_crtc_state); intel_encoders_post_disable(crtc, old_crtc_state, old_state); - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state); } @@ -6517,7 +6517,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); /* GDG double wide on either pipe, otherwise pipe A only */ - return INTEL_GEN(dev_priv) < 4 && + return INTEL_DISPLAY_GEN(dev_priv) < 4 && (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); } @@ -6577,7 +6577,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int clock_limit = dev_priv->max_dotclk_freq; - if (INTEL_GEN(dev_priv) < 4) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4) { clock_limit = dev_priv->max_cdclk_freq * 9 / 10; /* @@ -6632,7 +6632,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ - if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && + if ((INTEL_DISPLAY_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) return -EINVAL; @@ -6789,7 +6789,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, * Strictly speaking some registers are available before * gen7, but we only support DRRS on gen7+ */ - return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); + return IS_DISPLAY_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); } static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, @@ -6801,7 +6801,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta enum pipe pipe = crtc->pipe; enum transcoder transcoder = crtc_state->cpu_transcoder; - if (INTEL_GEN(dev_priv) >= 5) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); @@ -7195,7 +7195,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -7209,7 +7209,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLL_VCO_ENABLE; crtc_state->dpll_hw_state.dpll = dpll; - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { u32 dpll_md = (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc_state->dpll_hw_state.dpll_md = dpll_md; @@ -7283,7 +7283,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) vsyncshift += adjusted_mode->crtc_htotal; } - if (INTEL_GEN(dev_priv) > 3) + if (INTEL_DISPLAY_GEN(dev_priv) > 3) I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); I915_WRITE(HTOTAL(cpu_transcoder), @@ -7443,7 +7443,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) } if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (INTEL_GEN(dev_priv) < 4 || + if (INTEL_DISPLAY_GEN(dev_priv) < 4 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; else @@ -7654,7 +7654,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); uint32_t tmp; - if (INTEL_GEN(dev_priv) <= 3 && + if (INTEL_DISPLAY_GEN(dev_priv) <= 3 && (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) return; @@ -7663,7 +7663,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, return; /* Check whether the pfit is attached to our pipe. */ - if (INTEL_GEN(dev_priv) < 4) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4) { if (crtc->pipe != PIPE_B) return; } else { @@ -7734,7 +7734,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, val = I915_READ(DSPCNTR(i9xx_plane)); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -7748,7 +7748,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { offset = I915_READ(DSPOFFSET(i9xx_plane)); base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(i9xx_plane)); else @@ -7820,7 +7820,7 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc, pipe_config->lspcon_downsampling = false; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 9) { u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { @@ -7897,7 +7897,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; - if (INTEL_GEN(dev_priv) < 4) + if (INTEL_DISPLAY_GEN(dev_priv) < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; intel_get_pipe_timings(crtc, pipe_config); @@ -7905,7 +7905,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { /* No way to read it out on pipes B and C */ if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; @@ -8464,7 +8464,7 @@ static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state) struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 9) { u32 val = 0; switch (crtc_state->pipe_bpp) { @@ -8697,7 +8697,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (INTEL_GEN(dev_priv) >= 5) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) { m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) @@ -8806,7 +8806,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, val = I915_READ(PLANE_CTL(pipe, plane_id)); - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; else pixel_format = val & PLANE_CTL_FORMAT_MASK; @@ -8895,7 +8895,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, /* We currently do not free assignements of panel fitters on * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ - if (IS_GEN7(dev_priv)) { + if (IS_DISPLAY_GEN7(dev_priv)) { WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); } @@ -9491,7 +9491,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - if (INTEL_GEN(dev_priv) < 9 && + if (INTEL_DISPLAY_GEN(dev_priv) < 9 && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -9545,7 +9545,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -9857,17 +9857,17 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 cntl = 0; - if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (IS_DISPLAY_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; - if (INTEL_GEN(dev_priv) <= 10) { + if (INTEL_DISPLAY_GEN(dev_priv) <= 10) { cntl |= MCURSOR_GAMMA_ENABLE; if (HAS_DDI(dev_priv)) cntl |= MCURSOR_PIPE_CSC_ENABLE; } - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); switch (plane_state->base.crtc_w) { @@ -10072,7 +10072,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, ret = val & MCURSOR_MODE; - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) *pipe = plane->pipe; else *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> @@ -10572,7 +10572,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat struct drm_framebuffer *fb = plane_state->fb; int ret; - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { ret = skl_update_scaler_plane( to_intel_crtc_state(crtc_state), to_intel_plane_state(plane_state)); @@ -10621,21 +10621,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat turn_off, turn_on, mode_changed); if (turn_on) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) pipe_config->update_wm_pre = true; /* must disable cxsr around plane enable/disable */ if (plane->id != PLANE_CURSOR) pipe_config->disable_cxsr = true; } else if (turn_off) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) pipe_config->update_wm_post = true; /* must disable cxsr around plane enable/disable */ if (plane->id != PLANE_CURSOR) pipe_config->disable_cxsr = true; } else if (intel_wm_need_update(&plane->base, plane_state)) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { + if (INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { /* FIXME bollocks */ pipe_config->update_wm_pre = true; pipe_config->update_wm_post = true; @@ -10676,7 +10676,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat * the w/a on all three platforms. */ if (plane->id == PLANE_SPRITE0 && - (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) || + (IS_DISPLAY_GEN5(dev_priv) || IS_DISPLAY_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) && (turn_on || (!needs_scaling(old_plane_state) && needs_scaling(to_intel_plane_state(plane_state))))) @@ -10747,7 +10747,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) struct intel_plane_state *plane_state; int i; - if (INTEL_GEN(dev_priv) < 11) + if (INTEL_DISPLAY_GEN(dev_priv) < 11) return 0; /* @@ -10870,11 +10870,11 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, return ret; } } else if (dev_priv->display.compute_intermediate_wm) { - if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) + if (HAS_PCH_SPLIT(dev_priv) && INTEL_DISPLAY_GEN(dev_priv) < 9) pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; } - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -10962,7 +10962,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc, if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) bpp = 10*3; - else if (INTEL_GEN(dev_priv) >= 5) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 5) bpp = 12*3; else bpp = 8*3; @@ -11118,7 +11118,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config->pixel_rate); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", crtc->num_scalers, pipe_config->scaler_state.scaler_users, @@ -11159,7 +11159,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, plane->base.id, plane->name, fb->base.id, fb->width, fb->height, drm_get_format_name(fb->format->format, &format_name)); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", state->scaler_id, state->base.src.x1 >> 16, @@ -11648,7 +11648,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(lane_count); PIPE_CONF_CHECK_X(lane_lat_optim_mask); - if (INTEL_GEN(dev_priv) < 8) { + if (INTEL_DISPLAY_GEN(dev_priv) < 8) { PIPE_CONF_CHECK_M_N(dp_m_n); if (current_config->has_drrs) @@ -11675,7 +11675,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(pixel_multiplier); PIPE_CONF_CHECK_I(output_format); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); - if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || + if ((INTEL_DISPLAY_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) PIPE_CONF_CHECK_BOOL(limited_color_range); @@ -11701,7 +11701,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(gmch_pfit.control); /* pfit ratios are autocomputed by the hw on gen4+ */ - if (INTEL_GEN(dev_priv) < 4) + if (INTEL_DISPLAY_GEN(dev_priv) < 4) PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); @@ -11757,7 +11757,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) + if (IS_G4X(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 5) PIPE_CONF_CHECK_I(pipe_bpp); PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); @@ -11807,7 +11807,7 @@ static void verify_wm_state(struct drm_crtc *crtc, const enum pipe pipe = intel_crtc->pipe; int plane, level, max_level = ilk_wm_max_level(dev_priv); - if (INTEL_GEN(dev_priv) < 9 || !new_state->active) + if (INTEL_DISPLAY_GEN(dev_priv) < 9 || !new_state->active) return; skl_pipe_wm_get_hw_state(crtc, &hw_wm); @@ -11816,7 +11816,7 @@ static void verify_wm_state(struct drm_crtc *crtc, skl_ddb_get_hw_state(dev_priv, &hw_ddb); sw_ddb = &dev_priv->wm.skl_hw.ddb; - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) if (hw_ddb.enabled_slices != sw_ddb->enabled_slices) DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n", sw_ddb->enabled_slices, @@ -12649,7 +12649,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; /* If 2nd DBuf slice required, enable it here */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices); /* @@ -12704,7 +12704,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) } while (progress); /* If 2nd DBuf slice is no more required disable it */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices); } @@ -12828,7 +12828,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) * * No clue what this is supposed to achieve. */ - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) dev_priv->display.initial_watermarks(intel_state, new_intel_crtc_state); } @@ -13023,7 +13023,7 @@ static int intel_atomic_commit(struct drm_device *dev, * FIXME doing watermarks and fb cleanup from a vblank worker * (assuming we had any) would solve these problems. */ - if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { + if (INTEL_DISPLAY_GEN(dev_priv) < 9 && state->legacy_cursor_update) { struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int i; @@ -13132,7 +13132,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc, if (!dma_fence_is_i915(fence)) return; - if (INTEL_GEN(to_i915(crtc->dev)) < 6) + if (INTEL_DISPLAY_GEN(to_i915(crtc->dev)) < 6) return; if (drm_crtc_vblank_get(crtc)) @@ -13412,7 +13412,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, if (intel_cstate->update_pipe) intel_update_pipe_config(old_intel_cstate, intel_cstate); - else if (INTEL_GEN(dev_priv) >= 9) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 9) skl_detach_scalers(intel_cstate); out: @@ -13700,7 +13700,7 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, else if (IS_IVYBRIDGE(dev_priv)) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || i9xx_plane == PLANE_C; - else if (INTEL_GEN(dev_priv) >= 4) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; else return i9xx_plane == PLANE_A; @@ -13718,7 +13718,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) return skl_universal_plane_create(dev_priv, pipe, PLANE_PRIMARY); @@ -13731,7 +13731,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS * port is hooked to pipe B. Hence we want plane A feeding pipe B. */ - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) + if (HAS_FBC(dev_priv) && INTEL_DISPLAY_GEN(dev_priv) < 4) plane->i9xx_plane = (enum i9xx_plane_id) !pipe; else plane->i9xx_plane = (enum i9xx_plane_id) pipe; @@ -13745,7 +13745,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; } - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); modifiers = i9xx_format_modifiers; @@ -13773,7 +13773,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) possible_crtcs = BIT(pipe); - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, possible_crtcs, plane_funcs, formats, num_formats, modifiers, @@ -13793,14 +13793,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; } else { supported_rotations = DRM_MODE_ROTATE_0; } - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, supported_rotations); @@ -13864,7 +13864,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) drm_plane_create_rotation_property(&cursor->base, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | @@ -13964,7 +13964,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv->pipe_to_crtc_mapping[pipe] != NULL); dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc; - if (INTEL_GEN(dev_priv) < 9) { + if (INTEL_DISPLAY_GEN(dev_priv) < 9) { enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || @@ -14033,7 +14033,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) if ((I915_READ(DP_A) & DP_DETECTED) == 0) return false; - if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) + if (IS_DISPLAY_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) return false; return true; @@ -14041,7 +14041,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) static bool intel_crt_present(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) return false; if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) @@ -14424,7 +14424,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } /* fall through */ case I915_FORMAT_MOD_Y_TILED: - if (INTEL_GEN(dev_priv) < 9) { + if (INTEL_DISPLAY_GEN(dev_priv) < 9) { DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", mode_cmd->modifier[0]); goto err; @@ -14443,7 +14443,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * gen2/3 display engine uses the fence if present, * so the tiling mode must match the fb modifier exactly. */ - if (INTEL_GEN(dev_priv) < 4 && + if (INTEL_DISPLAY_GEN(dev_priv) < 4 && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); goto err; @@ -14477,7 +14477,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - if (INTEL_GEN(dev_priv) > 3) { + if (INTEL_DISPLAY_GEN(dev_priv) > 3) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14485,7 +14485,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, break; case DRM_FORMAT_ABGR8888: if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - INTEL_GEN(dev_priv) < 9) { + INTEL_DISPLAY_GEN(dev_priv) < 9) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14494,7 +14494,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: - if (INTEL_GEN(dev_priv) < 4) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14511,14 +14511,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { + if (INTEL_DISPLAY_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; } break; case DRM_FORMAT_NV12: - if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) || + if (INTEL_DISPLAY_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, @@ -14565,7 +14565,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + if (IS_DISPLAY_GEN9(dev_priv) && i == 0 && fb->width > 3840 && is_ccs_modifier(fb->modifier)) stride_alignment *= 4; @@ -14665,13 +14665,13 @@ intel_mode_valid(struct drm_device *dev, DRM_MODE_FLAG_CLKDIV2)) return MODE_BAD; - if (INTEL_GEN(dev_priv) >= 9 || + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; htotal_max = 8192; vtotal_max = 8192; - } else if (INTEL_GEN(dev_priv) >= 3) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 3) { hdisplay_max = 4096; vdisplay_max = 4096; htotal_max = 8192; @@ -14718,7 +14718,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { intel_init_cdclk_hooks(dev_priv); - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = skylake_get_initial_plane_config; @@ -14786,9 +14786,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.crtc_disable = i9xx_crtc_disable; } - if (IS_GEN5(dev_priv)) { + if (IS_DISPLAY_GEN5(dev_priv)) { dev_priv->display.fdi_link_train = ironlake_fdi_link_train; - } else if (IS_GEN6(dev_priv)) { + } else if (IS_DISPLAY_GEN6(dev_priv)) { dev_priv->display.fdi_link_train = gen6_fdi_link_train; } else if (IS_IVYBRIDGE(dev_priv)) { /* FIXME: detect B0+ stepping and use auto training */ @@ -14797,7 +14797,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.fdi_link_train = hsw_fdi_link_train; } - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; @@ -14920,12 +14920,12 @@ static void sanitize_watermarks(struct drm_device *dev) static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) { - if (IS_GEN5(dev_priv)) { + if (IS_DISPLAY_GEN5(dev_priv)) { u32 fdi_pll_clk = I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; - } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { + } else if (IS_DISPLAY_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { dev_priv->fdi_pll_freq = 270000; } else { return; @@ -15034,7 +15034,7 @@ int intel_modeset_init(struct drm_device *dev) if (IS_GEN2(dev_priv)) { dev->mode_config.max_width = 2048; dev->mode_config.max_height = 2048; - } else if (IS_GEN3(dev_priv)) { + } else if (IS_DISPLAY_GEN3(dev_priv)) { dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; } else { @@ -15225,7 +15225,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) { struct intel_crtc *crtc; - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) return; for_each_intel_crtc(&dev_priv->drm, crtc) { @@ -15715,7 +15715,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 9) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); @@ -15833,7 +15833,7 @@ void intel_modeset_cleanup(struct drm_device *dev) */ int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) { - unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; + unsigned reg = INTEL_DISPLAY_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; u16 gmch_ctrl; if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { @@ -15938,13 +15938,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) error->plane[i].control = I915_READ(DSPCNTR(i)); error->plane[i].stride = I915_READ(DSPSTRIDE(i)); - if (INTEL_GEN(dev_priv) <= 3) { + if (INTEL_DISPLAY_GEN(dev_priv) <= 3) { error->plane[i].size = I915_READ(DSPSIZE(i)); error->plane[i].pos = I915_READ(DSPPOS(i)); } - if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) error->plane[i].addr = I915_READ(DSPADDR(i)); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { error->plane[i].surface = I915_READ(DSPSURF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); } @@ -16009,13 +16009,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, err_printf(m, "Plane [%d]:\n", i); err_printf(m, " CNTR: %08x\n", error->plane[i].control); err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); - if (INTEL_GEN(dev_priv) <= 3) { + if (INTEL_DISPLAY_GEN(dev_priv) <= 3) { err_printf(m, " SIZE: %08x\n", error->plane[i].size); err_printf(m, " POS: %08x\n", error->plane[i].pos); } - if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) err_printf(m, " ADDR: %08x\n", error->plane[i].addr); - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { err_printf(m, " SURF: %08x\n", error->plane[i].surface); err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6b37d66194a3..eb7bc71c984c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -452,10 +452,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); - if (INTEL_GEN(dev_priv) >= 10) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 10) { source_rates = cnl_rates; size = ARRAY_SIZE(cnl_rates); - if (IS_GEN10(dev_priv)) + if (IS_DISPLAY_GEN10(dev_priv)) max_rate = cnl_max_source_rate(intel_dp); else max_rate = icl_max_source_rate(intel_dp); @@ -1206,7 +1206,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, to_i915(intel_dig_port->base.base.dev); uint32_t precharge, timeout; - if (IS_GEN6(dev_priv)) + if (IS_DISPLAY_GEN6(dev_priv)) precharge = 3; else precharge = 5; @@ -1694,7 +1694,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux_ch = intel_aux_ch(intel_dp); intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp); - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; intel_dp->aux_ch_data_reg = skl_aux_data_reg; } else if (HAS_PCH_SPLIT(dev_priv)) { @@ -1705,7 +1705,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux_ch_data_reg = g4x_aux_data_reg; } - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -1714,7 +1714,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -2102,7 +2102,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { int ret; ret = skl_update_scaler_crtc(pipe_config); @@ -2555,7 +2555,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) pp_ctrl_reg = _pp_ctrl_reg(intel_dp); pp = ironlake_get_pp_control(intel_dp); - if (IS_GEN5(dev_priv)) { + if (IS_DISPLAY_GEN5(dev_priv)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2563,7 +2563,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) } pp |= PANEL_POWER_ON; - if (!IS_GEN5(dev_priv)) + if (!IS_DISPLAY_GEN5(dev_priv)) pp |= PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2572,7 +2572,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) wait_panel_on(intel_dp); intel_dp->last_power_on = jiffies; - if (IS_GEN5(dev_priv)) { + if (IS_DISPLAY_GEN5(dev_priv)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); @@ -2800,7 +2800,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp, * 1. Wait for the start of vertical blank on the enabled pipe going to FDI * 2. Program DP PLL enable */ - if (IS_GEN5(dev_priv)) + if (IS_DISPLAY_GEN5(dev_priv)) intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); intel_dp->DP |= DP_PLL_ENABLE; @@ -3790,7 +3790,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) uint32_t signal_levels, mask = 0; uint8_t train_set = intel_dp->train_set[0]; - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (IS_GEN9_LP(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 10) { signal_levels = bxt_signal_levels(intel_dp); } else if (HAS_DDI(dev_priv)) { signal_levels = ddi_signal_levels(intel_dp); @@ -3802,7 +3802,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { signal_levels = ivb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; - } else if (IS_GEN6(dev_priv) && port == PORT_A) { + } else if (IS_DISPLAY_GEN6(dev_priv) && port == PORT_A) { signal_levels = snb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { @@ -5038,19 +5038,19 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) return g4x_digital_port_connected(encoder); } - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) return icl_digital_port_connected(encoder); - else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) + else if (IS_DISPLAY_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) return spt_digital_port_connected(encoder); else if (IS_GEN9_LP(dev_priv)) return bxt_digital_port_connected(encoder); - else if (IS_GEN8(dev_priv)) + else if (IS_DISPLAY_GEN8(dev_priv)) return bdw_digital_port_connected(encoder); - else if (IS_GEN7(dev_priv)) + else if (IS_DISPLAY_GEN7(dev_priv)) return ivb_digital_port_connected(encoder); - else if (IS_GEN6(dev_priv)) + else if (IS_DISPLAY_GEN6(dev_priv)) return snb_digital_port_connected(encoder); - else if (IS_GEN5(dev_priv)) + else if (IS_DISPLAY_GEN5(dev_priv)) return ilk_digital_port_connected(encoder); MISSING_CASE(INTEL_GEN(dev_priv)); @@ -5720,10 +5720,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) * eDP not supported on g4x. so bail out early just * for a bit extra safety in case the VBT is bonkers. */ - if (INTEL_GEN(dev_priv) < 5) + if (INTEL_DISPLAY_GEN(dev_priv) < 5) return false; - if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) + if (INTEL_DISPLAY_GEN(dev_priv) < 9 && port == PORT_A) return true; return intel_bios_is_port_edp(dev_priv, port); @@ -6092,7 +6092,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, return; } - if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { switch (index) { case DRRS_HIGH_RR: intel_dp_set_m_n(crtc_state, M1_N1); @@ -6104,7 +6104,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, default: DRM_ERROR("Unsupported refreshrate type\n"); } - } else if (INTEL_GEN(dev_priv) > 6) { + } else if (INTEL_DISPLAY_GEN(dev_priv) > 6) { i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); u32 val; @@ -6377,7 +6377,7 @@ intel_dp_drrs_init(struct intel_connector *connector, INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); mutex_init(&dev_priv->drrs.mutex); - if (INTEL_GEN(dev_priv) <= 6) { + if (INTEL_DISPLAY_GEN(dev_priv) <= 6) { DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); return NULL; } diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 7bdff5ba58b9..e582f36ab3ee 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -211,7 +211,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) unsigned int crtc_mask = drm_crtc_mask(&crtc->base); /* PCH only available on ILK+ */ - if (INTEL_GEN(dev_priv) < 5) + if (INTEL_DISPLAY_GEN(dev_priv) < 5) return; if (pll == NULL) @@ -1872,7 +1872,7 @@ static void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - if (INTEL_GEN(dev_priv) < 9) { + if (INTEL_DISPLAY_GEN(dev_priv) < 9) { uint32_t val = I915_READ(LCPLL_CTL); /* @@ -2213,7 +2213,7 @@ int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv) * For ICL+, the spec states: if reference frequency is 38.4, * use 19.2 because the DPLL automatically divides that by 2. */ - if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11 && ref_clock == 38400) ref_clock = 19200; return ref_clock; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index b019b5d3248a..cd8ed42d3444 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -48,7 +48,7 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv) static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) <= 3; + return INTEL_DISPLAY_GEN(dev_priv) <= 3; } /* @@ -84,9 +84,9 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, int lines; intel_fbc_get_plane_source_size(cache, NULL, &lines); - if (IS_GEN7(dev_priv)) + if (IS_DISPLAY_GEN7(dev_priv)) lines = min(lines, 2048); - else if (INTEL_GEN(dev_priv) >= 8) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 8) lines = min(lines, 2560); /* Hardware needs the full buffer stride, not just the active area. */ @@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) I915_WRITE(FBC_TAG(i), 0); - if (IS_GEN4(dev_priv)) { + if (IS_DISPLAY_GEN4(dev_priv)) { u32 fbc_ctl2; /* Set it up... */ @@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) if (params->flags & PLANE_HAS_FENCE) { dpfc_ctl |= DPFC_CTL_FENCE_EN; - if (IS_GEN5(dev_priv)) + if (IS_DISPLAY_GEN5(dev_priv)) dpfc_ctl |= params->vma->fence->id; - if (IS_GEN6(dev_priv)) { + if (IS_DISPLAY_GEN6(dev_priv)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | params->vma->fence->id); @@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) params->crtc.fence_y_offset); } } else { - if (IS_GEN6(dev_priv)) { + if (IS_DISPLAY_GEN6(dev_priv)) { I915_WRITE(SNB_DPFC_CTL_SA, 0); I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); } @@ -347,7 +347,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 5) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) return ilk_fbc_is_active(dev_priv); else if (IS_GM45(dev_priv)) return g4x_fbc_is_active(dev_priv); @@ -361,9 +361,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) fbc->active = true; - if (INTEL_GEN(dev_priv) >= 7) + if (INTEL_DISPLAY_GEN(dev_priv) >= 7) gen7_fbc_activate(dev_priv); - else if (INTEL_GEN(dev_priv) >= 5) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 5) ilk_fbc_activate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_activate(dev_priv); @@ -377,7 +377,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) fbc->active = false; - if (INTEL_GEN(dev_priv) >= 5) + if (INTEL_DISPLAY_GEN(dev_priv) >= 5) ilk_fbc_deactivate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_deactivate(dev_priv); @@ -470,7 +470,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, 4096, 0, end); - if (ret && INTEL_GEN(dev_priv) <= 4) { + if (ret && INTEL_DISPLAY_GEN(dev_priv) <= 4) { return 0; } else if (ret) { compression_threshold <<= 1; @@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, if (stride < 512) return false; - if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) + if (IS_GEN2(dev_priv) || IS_DISPLAY_GEN3(dev_priv)) return stride == 4096 || stride == 8192; - if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) + if (IS_DISPLAY_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) return false; if (stride > 16384) @@ -626,10 +626,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) struct intel_fbc *fbc = &dev_priv->fbc; unsigned int effective_w, effective_h, max_w, max_h; - if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { max_w = 4096; max_h = 4096; - } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + } else if (IS_G4X(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 5) { max_w = 4096; max_h = 2048; } else { @@ -734,7 +734,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } - if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && + if (INTEL_DISPLAY_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && cache->plane.rotation != DRM_MODE_ROTATE_0) { fbc->no_fbc_reason = "rotation unsupported"; return false; @@ -1275,7 +1275,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + if (IS_BROADWELL(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 9) return 1; return 0; @@ -1321,7 +1321,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) } /* This value was pulled out of someone's hat */ - if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) + if (INTEL_DISPLAY_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); /* We still don't have any sort of hardware state readout for FBC, so diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index 77c123cc8817..2d5892b03623 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -260,11 +260,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (IS_DISPLAY_GEN5(dev_priv) || IS_DISPLAY_GEN6(dev_priv)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); - else if (IS_GEN7(dev_priv)) + else if (IS_DISPLAY_GEN7(dev_priv)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (INTEL_GEN(dev_priv) >= 8) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 8) broadwell_set_fifo_underrun_reporting(dev, pipe, enable); return old; @@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_check_fifo_underruns(crtc); - else if (IS_GEN7(dev_priv)) + else if (IS_DISPLAY_GEN7(dev_priv)) ivybridge_check_fifo_underruns(crtc); } diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index 1bf487f94254..c11cc26983fa 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -768,7 +768,7 @@ static void intel_hdcp_prop_work(struct work_struct *work) bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) { /* PORT E doesn't have HDCP, and PORT F is disabled */ - return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && + return ((INTEL_DISPLAY_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && !IS_CHERRYVIEW(dev_priv) && port < PORT_E); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 206a4c18863c..5f07c26d32e5 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1478,9 +1478,9 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) if (INTEL_DISPLAY_GEN(dev_priv) >= 10) max_tmds_clock = 594000; - else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) max_tmds_clock = 300000; - else if (INTEL_GEN(dev_priv) >= 5) + else if (INTEL_DISPLAY_GEN(dev_priv) >= 5) max_tmds_clock = 225000; else max_tmds_clock = 165000; @@ -1579,7 +1579,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, true, force_dvi); /* if we can't do 8,12bpc we may still be able to do 10bpc */ - if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) + if (status != MODE_OK && INTEL_DISPLAY_GEN(dev_priv) >= 11) status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, true, force_dvi); } @@ -1600,7 +1600,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, if (HAS_GMCH_DISPLAY(dev_priv)) return false; - if (bpc == 10 && INTEL_GEN(dev_priv) < 11) + if (bpc == 10 && INTEL_DISPLAY_GEN(dev_priv) < 11) return false; if (crtc_state->pipe_bpp <= 8*3) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 33d87ab93fdd..8ffc7d48eb31 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -362,7 +362,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) static inline unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : + return INTEL_DISPLAY_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : GMBUS_BYTE_COUNT_MAX; } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e6c5d985ea0a..3fb67ca55da4 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -129,12 +129,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; - if (INTEL_GEN(dev_priv) < 5) + if (INTEL_DISPLAY_GEN(dev_priv) < 5) pipe_config->gmch_pfit.lvds_border_bits = tmp & LVDS_BORDER_ENABLE; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_GEN(dev_priv) < 4) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4) { tmp = I915_READ(PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; @@ -179,7 +179,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, /* Convert from 100ms to 100us units */ pps->t4 = val * 1000; - if (INTEL_GEN(dev_priv) <= 4 && + if (INTEL_DISPLAY_GEN(dev_priv) <= 4 && pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { DRM_DEBUG_KMS("Panel power timings uninitialized, " "setting defaults\n"); @@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, * special lvds dither control bit on pch-split platforms, dithering is * only controlled through the PIPECONF reg. */ - if (IS_GEN4(dev_priv)) { + if (IS_DISPLAY_GEN4(dev_priv)) { /* * Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. @@ -393,7 +393,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, unsigned int lvds_bpp; /* Should never happen!! */ - if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { + if (INTEL_DISPLAY_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { DRM_ERROR("Can't support LVDS on pipe A\n"); return false; } @@ -810,7 +810,7 @@ static bool intel_lvds_supported(struct drm_i915_private *dev_priv) * Otherwise LVDS was only attached to mobile products, * except for the inglorious 830gm */ - if (INTEL_GEN(dev_priv) <= 4 && + if (INTEL_DISPLAY_GEN(dev_priv) <= 4 && IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) return true; @@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->cloneable = 0; if (HAS_PCH_SPLIT(dev_priv)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); - else if (IS_GEN4(dev_priv)) + else if (IS_DISPLAY_GEN4(dev_priv)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1); else intel_encoder->crtc_mask = (1 << 1); diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 72eb7e48e8bc..ae8ad30a5abd 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -897,7 +897,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) /* XXX: This is not the same logic as in the xorg driver, but more in * line with the intel documentation for the i965 */ - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { /* on i965 use the PGM reg to read out the autoscaler values */ ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; } else { @@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv, if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) return -EINVAL; - if (IS_GEN4(dev_priv) && rec->stride_Y < 512) + if (IS_DISPLAY_GEN4(dev_priv) && rec->stride_Y < 512) return -EINVAL; tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index ad88008f8dd0..c4cfc5656c79 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -326,7 +326,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, break; case DRM_MODE_SCALE_ASPECT: /* Scale but preserve the aspect ratio */ - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) i965_scale_aspect(pipe_config, &pfit_control); else i9xx_scale_aspect(pipe_config, &pfit_control, @@ -340,7 +340,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { pfit_control |= PFIT_ENABLE; - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) pfit_control |= PFIT_SCALING_AUTO; else pfit_control |= (VERT_AUTO_SCALE | @@ -356,7 +356,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, /* 965+ wants fuzzy fitting */ /* FIXME: handle multiple panels by failing gracefully */ - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | PFIT_FILTER_FUZZY); @@ -367,7 +367,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, } /* Make sure pre-965 set dither correctly for 18bpp panels. */ - if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) + if (INTEL_DISPLAY_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) pfit_control |= PANEL_8TO6_DITHER_ENABLE; pipe_config->gmch_pfit.control = pfit_control; @@ -481,7 +481,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector) u32 val; val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; - if (INTEL_GEN(dev_priv) < 4) + if (INTEL_DISPLAY_GEN(dev_priv) < 4) val >>= 1; if (panel->backlight.combination_mode) { @@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); } - if (IS_GEN4(dev_priv)) { + if (IS_DISPLAY_GEN4(dev_priv)) { mask = BACKLIGHT_DUTY_CYCLE_MASK; } else { level <<= 1; @@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) panel->backlight.get = vlv_get_backlight; panel->backlight.hz_to_pwm = vlv_hz_to_pwm; } - } else if (IS_GEN4(dev_priv)) { + } else if (IS_DISPLAY_GEN4(dev_priv)) { panel->backlight.setup = i965_setup_backlight; panel->backlight.enable = i965_enable_backlight; panel->backlight.disable = i965_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index d24f8e1b0e37..c9cbf4db805c 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -91,7 +91,7 @@ void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) | EDP_PSR_PRE_ENTRY(TRANSCODER_EDP); - if (INTEL_GEN(dev_priv) >= 8) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 8) { mask |= EDP_PSR_ERROR(TRANSCODER_A) | EDP_PSR_ERROR(TRANSCODER_B) | EDP_PSR_ERROR(TRANSCODER_C); @@ -153,7 +153,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) enum transcoder cpu_transcoder; ktime_t time_ns = ktime_get(); - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_DISPLAY_GEN(dev_priv) >= 8) transcoders |= BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C); @@ -175,7 +175,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", transcoder_name(cpu_transcoder)); - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) { u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); bool psr2_enabled = dev_priv->psr.psr2_enabled; @@ -242,7 +242,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) WARN_ON(dev_priv->psr.dp); dev_priv->psr.dp = intel_dp; - if (INTEL_GEN(dev_priv) >= 9 && + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; @@ -350,7 +350,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) if (dev_priv->psr.link_standby) dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) + if (!dev_priv->psr.psr2_enabled && INTEL_DISPLAY_GEN(dev_priv) >= 8) dpcd_val |= DP_PSR_CRC_VERIFICATION; drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); @@ -405,7 +405,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_DISPLAY_GEN(dev_priv) >= 8) val |= EDP_PSR_CRC_ENABLE; val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; @@ -466,7 +466,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (INTEL_DISPLAY_GEN(dev_priv) >= 10) { psr_max_h = 4096; psr_max_v = 2304; - } else if (IS_GEN9(dev_priv)) { + } else if (IS_DISPLAY_GEN9(dev_priv)) { psr_max_h = 3640; psr_max_v = 2304; } @@ -543,7 +543,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); WARN_ON(dev_priv->psr.active); @@ -594,7 +594,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, EDP_PSR_DEBUG_MASK_LPSP | EDP_PSR_DEBUG_MASK_MAX_SLEEP; - if (INTEL_GEN(dev_priv) < 11) + if (INTEL_DISPLAY_GEN(dev_priv) < 11) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; I915_WRITE(EDP_PSR_DEBUG, mask); @@ -1063,7 +1063,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv) return; if (i915_modparams.enable_psr == -1) - if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) + if (INTEL_DISPLAY_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) i915_modparams.enable_psr = 0; /* Set link_standby x link_off defaults */ diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 5805ec1aba12..7be9ad6f0d7f 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1344,13 +1344,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, return; /* Set the SDVO control regs. */ - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; - if (INTEL_GEN(dev_priv) < 5) + if (INTEL_DISPLAY_GEN(dev_priv) < 5) sdvox |= SDVO_BORDER_ENABLE; } else { sdvox = I915_READ(intel_sdvo->sdvo_reg); @@ -1367,11 +1367,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, sdvox |= SDVO_PIPE_SEL(crtc->pipe); if (crtc_state->has_audio) { - WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); + WARN_ON_ONCE(INTEL_DISPLAY_GEN(dev_priv) < 4); sdvox |= SDVO_AUDIO_ENABLE; } - if (INTEL_GEN(dev_priv) >= 4) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { @@ -1382,7 +1382,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - INTEL_GEN(dev_priv) < 5) + INTEL_DISPLAY_GEN(dev_priv) < 5) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } @@ -2451,7 +2451,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); intel_attach_force_audio_property(&connector->base.base); - if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { + if (INTEL_DISPLAY_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { intel_attach_broadcast_rgb_property(&connector->base.base); } intel_attach_aspect_ratio_property(&connector->base.base); @@ -2521,7 +2521,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) connector->connector_type = DRM_MODE_CONNECTOR_DVID; /* gen3 doesn't do the hdmi bits in the SDVO register */ - if (INTEL_GEN(dev_priv) >= 4 && + if (INTEL_DISPLAY_GEN(dev_priv) >= 4 && intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; intel_sdvo_connector->is_hdmi = true; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 6df12aa994d4..9aa9b4b5905e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -415,7 +415,7 @@ skl_program_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), (plane_state->color_plane[1].offset - surf_addr) | aux_stride); - if (INTEL_GEN(dev_priv) < 11) + if (INTEL_DISPLAY_GEN(dev_priv) < 11) I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); @@ -976,7 +976,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE; - if (IS_GEN6(dev_priv)) + if (IS_DISPLAY_GEN6(dev_priv)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -1207,7 +1207,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, int ret; if (intel_fb_scalable(plane_state->base.fb)) { - if (INTEL_GEN(dev_priv) < 7) { + if (INTEL_DISPLAY_GEN(dev_priv) < 7) { min_scale = 1; max_scale = 16 << 16; } else if (IS_IVYBRIDGE(dev_priv)) { @@ -1238,7 +1238,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, if (ret) return ret; - if (INTEL_GEN(dev_priv) >= 7) + if (INTEL_DISPLAY_GEN(dev_priv) >= 7) plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); else plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); @@ -1337,7 +1337,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ switch (fb->format->format) { case DRM_FORMAT_RGB565: - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) break; /* fall through */ case DRM_FORMAT_C8: @@ -1472,7 +1472,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9; + return INTEL_DISPLAY_GEN(dev_priv) >= 9; } static void intel_plane_set_ckey(struct intel_plane_state *plane_state, @@ -1496,7 +1496,7 @@ static void intel_plane_set_ckey(struct intel_plane_state *plane_state, * On SKL+ we want dst key enabled on * the primary and not on the sprite. */ - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && set->flags & I915_SET_COLORKEY_DESTINATION) key->flags = 0; } @@ -1535,7 +1535,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * Also multiple planes can't do destination keying on the same * pipe simultaneously. */ - if (INTEL_GEN(dev_priv) >= 9 && + if (INTEL_DISPLAY_GEN(dev_priv) >= 9 && to_intel_plane(plane)->id >= PLANE_SPRITE1 && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; @@ -1865,7 +1865,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, enum pipe pipe, enum plane_id plane_id) { - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_DISPLAY_GEN(dev_priv) >= 11) return plane_id <= PLANE_SPRITE3; if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) @@ -1886,7 +1886,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, if (plane_id == PLANE_CURSOR) return false; - if (INTEL_GEN(dev_priv) >= 10) + if (INTEL_DISPLAY_GEN(dev_priv) >= 10) return true; if (IS_GEMINILAKE(dev_priv)) @@ -1996,7 +1996,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; - if (INTEL_GEN(dev_priv) >= 10) + if (INTEL_DISPLAY_GEN(dev_priv) >= 10) supported_rotations |= DRM_MODE_REFLECT_X; drm_plane_create_rotation_property(&plane->base, @@ -2040,7 +2040,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_DISPLAY_GEN(dev_priv) >= 9) return skl_universal_plane_create(dev_priv, pipe, PLANE_SPRITE0 + sprite); @@ -2060,7 +2060,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, modifiers = i9xx_plane_format_modifiers; plane_funcs = &vlv_sprite_funcs; - } else if (INTEL_GEN(dev_priv) >= 7) { + } else if (INTEL_DISPLAY_GEN(dev_priv) >= 7) { plane->max_stride = g4x_sprite_max_stride; plane->update_plane = ivb_update_plane; plane->disable_plane = ivb_disable_plane; @@ -2080,7 +2080,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->check_plane = g4x_sprite_check; modifiers = i9xx_plane_format_modifiers; - if (IS_GEN6(dev_priv)) { + if (IS_DISPLAY_GEN6(dev_priv)) { formats = snb_plane_formats; num_formats = ARRAY_SIZE(snb_plane_formats); diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 860f306a23ba..afbaa582d147 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1069,7 +1069,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, set_color_conversion(dev_priv, color_conversion); - if (INTEL_GEN(dev_priv) >= 4) + if (INTEL_DISPLAY_GEN(dev_priv) >= 4) I915_WRITE(TV_CLR_KNOBS, 0x00404000); else I915_WRITE(TV_CLR_KNOBS, 0x00606000);

[RFC,4/4] drm/i915: Expand DISPLAY_GEN macro usage to display related files.

Commit Message

Patch