From patchwork Wed Oct 31 00:45:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10661937 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F33CD13BF for ; Wed, 31 Oct 2018 00:51:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E355A2A2E1 for ; Wed, 31 Oct 2018 00:51:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D7B672A370; Wed, 31 Oct 2018 00:51:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 840392A2E1 for ; Wed, 31 Oct 2018 00:51:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 67DCA6E20D; Wed, 31 Oct 2018 00:51:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B0B76E010 for ; Wed, 31 Oct 2018 00:51:16 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2018 17:51:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,446,1534834800"; d="scan'208";a="270138341" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga005.jf.intel.com with ESMTP; 30 Oct 2018 17:51:15 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 30 Oct 2018 17:45:14 -0700 Message-Id: <20181031004517.17250-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031004517.17250-1-anusha.srivatsa@intel.com> References: <20181031004517.17250-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v4 4/7] i915/dp/fec: Add fec_enable to the crtc state. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error correction on other scenarios too if needed. v2: - Control compression_enable with the fec_enable parameter in crtc state and with intel_dp_supports_fec() (Ville) - intel_dp_can_fec()/intel_dp_supports_fec()(manasi) Suggested-by: Ville Syrjala Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dp.c | 25 ++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a344be555dd6..5ae3855925f3 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2045,6 +2045,21 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, return false; } +static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; + + return INTEL_GEN(dev_priv) >= 11 && port != PORT_A; +} + +static bool intel_dp_supports_fec(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config) +{ + return intel_dp_source_supports_fec(intel_dp) && + drm_dp_sink_supports_fec(intel_dp->fec_capable); +} static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits) @@ -2056,6 +2071,8 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, u16 dsc_max_output_bpp = 0; u8 dsc_dp_slice_count = 0; + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp); + if (INTEL_GEN(dev_priv) < 10 || !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) return false; @@ -2122,7 +2139,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->dsc_params.compressed_bpp); return false; } - pipe_config->dsc_params.compression_enable = true; + + if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp, pipe_config)) { + DRM_DEBUG_KMS("No FEC Support, disabling Compression"); + pipe_config->dsc_params.compression_enable = false; + } else { + pipe_config->dsc_params.compression_enable = true; + } DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9a94c6544bf5..9f701463219b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -940,6 +940,9 @@ struct intel_crtc_state { u8 slice_count; } dsc_params; struct drm_dsc_config dp_dsc_cfg; + + /* Forward Error correction State */ + bool fec_enable; }; struct intel_crtc {