| Message ID | 20181031004517.17250-6-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Forward Error Correction | expand |
>-----Original Message----- >From: Srivatsa, Anusha >Sent: Tuesday, October 30, 2018 5:45 PM >To: intel-gfx@lists.freedesktop.org >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Singh, Gaurav K ><gaurav.k.singh@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>; Ville >Syrjala <ville.syrjala@linux.intel.com>; Navare, Manasi D ><manasi.d.navare@intel.com> >Subject: [v4 5/7] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION > >If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd >register: >FEC_CONFIGURATION. > >This has to happen before link training. > >v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready > - change commit message. (Gaurav) > >v3: rebased. (r-b Manasi) > >v4: Use fec crtc state, before setting FEC_READY bit. (Anusha) > >Cc: Gaurav K Singh <gaurav.k.singh@intel.com> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Manasi Navare <manasi.d.navare@intel.com> >Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_ddi.c | 1 + drivers/gpu/drm/i915/intel_dp.c | 18 >++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ > 3 files changed, 22 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >index 1de0a3917d7f..efbada95dc4e 100644 >--- a/drivers/gpu/drm/i915/intel_ddi.c >+++ b/drivers/gpu/drm/i915/intel_ddi.c >@@ -2932,6 +2932,7 @@ static void intel_ddi_pre_enable_dp(struct >intel_encoder *encoder, > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > intel_dp_sink_set_decompression_state(intel_dp, crtc_state, > DP_DECOMPRESSION_EN); >+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); > intel_dp_start_link_train(intel_dp); > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) > intel_dp_stop_link_train(intel_dp); >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >index 5ae3855925f3..a750415d1ec0 100644 >--- a/drivers/gpu/drm/i915/intel_dp.c >+++ b/drivers/gpu/drm/i915/intel_dp.c >@@ -3058,6 +3058,24 @@ void intel_dp_sink_set_decompression_state(struct >intel_dp *intel_dp, > state == DP_DECOMPRESSION_EN ? "enable" : >"disable"); } > >+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, >+ const struct intel_crtc_state *crtc_state, >+ int state) Manasi, Ville, Since enable_fec and disable_fec (next two patches in the series) are being moved to intel_ddi.c, this function might also be moved to intel_ddi.c? Anusha >+{ >+ int ret; >+ >+ if (!crtc_state->fec_enable) >+ return; >+ >+ /* If compression is not enabled, do not set FEC bits */ >+ if (!crtc_state->dsc_params.compression_enable) >+ return; >+ >+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, >state); >+ if (ret < 0) >+ DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n"); } >+ > /* If the sink supports it, try to set the power state appropriately */ void >intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >index 9f701463219b..2a080205968d 100644 >--- a/drivers/gpu/drm/i915/intel_drv.h >+++ b/drivers/gpu/drm/i915/intel_drv.h >@@ -1796,6 +1796,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int >mode); void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, > const struct intel_crtc_state >*crtc_state, > int state); >+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, >+ const struct intel_crtc_state *crtc_state, >+ int state); > void intel_dp_encoder_reset(struct drm_encoder *encoder); void >intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void >intel_dp_encoder_destroy(struct drm_encoder *encoder); >-- >2.17.1
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 1de0a3917d7f..efbada95dc4e 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2932,6 +2932,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_sink_set_decompression_state(intel_dp, crtc_state, DP_DECOMPRESSION_EN); + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); intel_dp_start_link_train(intel_dp); if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5ae3855925f3..a750415d1ec0 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3058,6 +3058,24 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, state == DP_DECOMPRESSION_EN ? "enable" : "disable"); } +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state) +{ + int ret; + + if (!crtc_state->fec_enable) + return; + + /* If compression is not enabled, do not set FEC bits */ + if (!crtc_state->dsc_params.compression_enable) + return; + + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state); + if (ret < 0) + DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n"); +} + /* If the sink supports it, try to set the power state appropriately */ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9f701463219b..2a080205968d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1796,6 +1796,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int state); +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder);
If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd register: FEC_CONFIGURATION. This has to happen before link training. v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready - change commit message. (Gaurav) v3: rebased. (r-b Manasi) v4: Use fec crtc state, before setting FEC_READY bit. (Anusha) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 1 + drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 22 insertions(+)