[v3] drm/i915/fia: FIA registers offset implementation.
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Message ID 20181031204121.4327-1-anusha.srivatsa@intel.com
State New
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Series
  • [v3] drm/i915/fia: FIA registers offset implementation.
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Commit Message

Srivatsa, Anusha Oct. 31, 2018, 8:41 p.m. UTC
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.

v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)

v3:
- Remove register offset defines. (Jani)
- Update comment. (Anusha)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Comments

Lucas De Marchi Oct. 31, 2018, 10:01 p.m. UTC | #1
On Wed, Oct 31, 2018 at 01:41:21PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
> 
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
> 
> v3:
> - Remove register offset defines. (Jani)
> - Update comment. (Anusha)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d089ef848b2..e80e9b983334 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,11 @@ enum i915_power_well_id {
>  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
> +/* FIA Bases */

Comment not needed: you have only one base.

With that:
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

> +#define FIA1_BASE			0x163000
> +
>  /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + 0x008C0)
>  #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
>  #define   DFLEXDPMLE1_DPMLETC(n, x)	((x) << (4 * (n)))
>  
> @@ -11031,17 +11034,17 @@ enum skl_power_gate {
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>  
> -#define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + 0x008A0)
>  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
>  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
>  #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
>  #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
>  #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
>  
> -#define PORT_TX_DFLEXDPPMS				_MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + 0x00890)
>  #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
>  
> -#define PORT_TX_DFLEXDPCSSS				_MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + 0x00894)
>  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
>  
>  #endif /* _I915_REG_H_ */
> -- 
> 2.17.1
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef848b2..e80e9b983334 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,11 @@  enum i915_power_well_id {
 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
+/* FIA Bases */
+#define FIA1_BASE			0x163000
+
 /* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + 0x008C0)
 #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
 #define   DFLEXDPMLE1_DPMLETC(n, x)	((x) << (4 * (n)))
 
@@ -11031,17 +11034,17 @@  enum skl_power_gate {
 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
 
-#define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + 0x008A0)
 #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
 #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
 #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
 #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
 #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
 
-#define PORT_TX_DFLEXDPPMS				_MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + 0x00890)
 #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
 
-#define PORT_TX_DFLEXDPCSSS				_MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
 
 #endif /* _I915_REG_H_ */