| Message ID | 20181031225944.1226-1-niklas.soderlund@ragnatech.se (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: renesas_sdhi: remove workaround for HS400 clock | expand |
On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > The driver sets an incorrect clock and depends on the clock driver > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > Instead of spreading the workaround between the two drivers the clock > driver should be made aware of the ES versions where the special clock > handling is needed no need to keep this workaround in the SDHI driver. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > The driver sets an incorrect clock and depends on the clock driver > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > Instead of spreading the workaround between the two drivers the clock > driver should be made aware of the ES versions where the special clock > handling is needed no need to keep this workaround in the SDHI driver. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > The driver sets an incorrect clock and depends on the clock driver > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > Instead of spreading the workaround between the two drivers the clock > driver should be made aware of the ES versions where the special clock > handling is needed no need to keep this workaround in the SDHI driver. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Does this change cause a regression pending an update to the clock driver?
Hi Simon, On 2018-11-02 12:55:02 +0100, Simon Horman wrote: > On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote: > > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > > > The driver sets an incorrect clock and depends on the clock driver > > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > > Instead of spreading the workaround between the two drivers the clock > > driver should be made aware of the ES versions where the special clock > > handling is needed no need to keep this workaround in the SDHI driver. > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Does this change cause a regression pending an update > to the clock driver? No it does not, the corresponding BSP commit to the clock driver [1] was never part of upstream. This change should never have been merged upstream as it uses the hack from the BSP clock driver. Also HS400 have never been enabled upstream for Gen3. 1. 11fca067bde0221d ("clk: renesas: rcar-gen3: Fix SD divider setting")
On Fri, Nov 02, 2018 at 01:42:47PM +0100, Niklas Söderlund wrote: > Hi Simon, > > On 2018-11-02 12:55:02 +0100, Simon Horman wrote: > > On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote: > > > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > > > > > The driver sets an incorrect clock and depends on the clock driver > > > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > > > Instead of spreading the workaround between the two drivers the clock > > > driver should be made aware of the ES versions where the special clock > > > handling is needed no need to keep this workaround in the SDHI driver. > > > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > > > Does this change cause a regression pending an update > > to the clock driver? > > No it does not, the corresponding BSP commit to the clock driver [1] was > never part of upstream. This change should never have been merged > upstream as it uses the hack from the BSP clock driver. Also HS400 have > never been enabled upstream for Gen3. > > 1. 11fca067bde0221d ("clk: renesas: rcar-gen3: Fix SD divider setting") Thanks, got it. Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
On 31 October 2018 at 23:59, Niklas Söderlund <niklas.soderlund@ragnatech.se> wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > The driver sets an incorrect clock and depends on the clock driver > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > Instead of spreading the workaround between the two drivers the clock > driver should be made aware of the ES versions where the special clock > handling is needed no need to keep this workaround in the SDHI driver. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/renesas_sdhi_core.c | 9 --------- > 1 file changed, 9 deletions(-) > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c > index d3ac43c3d0b655dc..78bd117bbe65de46 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -163,15 +163,6 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, > if (new_clock == 0) > goto out; > > - /* > - * Both HS400 and HS200/SD104 set 200MHz, but some devices need to > - * set 400MHz to distinguish the CPG settings in HS400. > - */ > - if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && > - host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && > - new_clock == 200000000) > - new_clock = 400000000; > - > clock = renesas_sdhi_clk_update(host, new_clock) / 512; > > for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) > -- > 2.19.1 >
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index d3ac43c3d0b655dc..78bd117bbe65de46 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -163,15 +163,6 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, if (new_clock == 0) goto out; - /* - * Both HS400 and HS200/SD104 set 200MHz, but some devices need to - * set 400MHz to distinguish the CPG settings in HS400. - */ - if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && - host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && - new_clock == 200000000) - new_clock = 400000000; - clock = renesas_sdhi_clk_update(host, new_clock) / 512; for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)