@@ -4012,6 +4012,9 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
*/
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ /* Clear fec_capable to avoid using stale values */
+ intel_dp->fec_capable = 0;
+
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4024,6 +4027,15 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
(int)sizeof(intel_dp->dsc_dpcd),
intel_dp->dsc_dpcd);
+ /* FEC is supported only on DP 1.4 */
+ if (!intel_dp_is_edp(intel_dp)) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+ &intel_dp->fec_capable) < 0)
+ DRM_ERROR("Failed to read FEC DPCD register\n");
+
+ DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
+ intel_dp->fec_capable);
+ }
}
}
@@ -1115,6 +1115,7 @@ struct intel_dp {
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+ u8 fec_capable;
/* source rates */
int num_source_rates;
const int *source_rates;