From patchwork Mon Nov 5 12:06:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 10668055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFE3B175A for ; Mon, 5 Nov 2018 12:07:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B079D28A26 for ; Mon, 5 Nov 2018 12:07:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4B7029753; Mon, 5 Nov 2018 12:07:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F23328A26 for ; Mon, 5 Nov 2018 12:07:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729804AbeKEV0W (ORCPT ); Mon, 5 Nov 2018 16:26:22 -0500 Received: from heliosphere.sirena.org.uk ([172.104.155.198]:53732 "EHLO heliosphere.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729789AbeKEV0W (ORCPT ); Mon, 5 Nov 2018 16:26:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=j4WhlVy+BFCj/6P2cuVWkTrLSISayI93pAx1nson1Ds=; b=JGMj8kTG61ic XnXu8aftnwRT2zbzCpb2Z97xJV9+h0GBLCH+2JIG8GeZGfm9Ebzh94pvVTRvS90Ps4V7i6ALk6COz NvgH0ZqS7wgoHA2navqae7csV3h9W+WMQ0knOymhLhWQidqZx4XDD0RmUd/M0K6z93wwQ9X02QUNW xVZqE=; Received: from cpc102320-sgyl38-2-0-cust46.18-2.cable.virginm.net ([82.37.168.47] helo=debutante.sirena.org.uk) by heliosphere.sirena.org.uk with esmtpa (Exim 4.89) (envelope-from ) id 1gJded-0008OO-GT; Mon, 05 Nov 2018 12:06:51 +0000 Received: by debutante.sirena.org.uk (Postfix, from userid 1000) id 28D0E1124D98; Mon, 5 Nov 2018 12:06:51 +0000 (GMT) From: Mark Brown To: Emil Renner Berthing Cc: Heiko Stuebner , Mark Brown , linux-spi@vger.kernel.org, Addy Ke , Mark Brown , Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Subject: Applied "spi: rockchip: always use SPI mode" to the spi tree In-Reply-To: <20181031105711.19575-4-esmil@mailme.dk> Message-Id: <20181105120651.28D0E1124D98@debutante.sirena.org.uk> Date: Mon, 5 Nov 2018 12:06:51 +0000 (GMT) Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: rockchip: always use SPI mode has been applied to the spi tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From 2410d6a3c3070e205169a1a741aa78898e30a642 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 31 Oct 2018 11:57:00 +0100 Subject: [PATCH] spi: rockchip: always use SPI mode The hardware supports 3 different variants of SPI and there were some code around it, but nothing to actually set it to anything but "Motorola SPI". Just drop that code and always use that mode. Signed-off-by: Emil Renner Berthing Tested-by: Heiko Stuebner Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 87d1b9837d94..7fac4253075e 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -156,12 +156,6 @@ #define ROCKCHIP_SPI_MAX_CS_NUM 2 -enum rockchip_ssi_type { - SSI_MOTO_SPI = 0, - SSI_TI_SSP, - SSI_NS_MICROWIRE, -}; - struct rockchip_spi_dma_data { struct dma_chan *ch; dma_addr_t addr; @@ -179,8 +173,6 @@ struct rockchip_spi { u32 fifo_len; /* max bus freq supported */ u32 max_freq; - /* supported slave numbers */ - enum rockchip_ssi_type type; u16 mode; u8 tmode; @@ -525,14 +517,14 @@ static void rockchip_spi_config(struct rockchip_spi *rs) u32 dmacr = 0; int rsd = 0; - u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) - | (CR0_SSD_ONE << CR0_SSD_OFFSET) - | (CR0_EM_BIG << CR0_EM_OFFSET); + u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET + | CR0_BHT_8BIT << CR0_BHT_OFFSET + | CR0_SSD_ONE << CR0_SSD_OFFSET + | CR0_EM_BIG << CR0_EM_OFFSET; cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); cr0 |= (rs->tmode << CR0_XFM_OFFSET); - cr0 |= (rs->type << CR0_FRF_OFFSET); if (rs->use_dma) { if (rs->tx) @@ -709,7 +701,6 @@ static int rockchip_spi_probe(struct platform_device *pdev) spi_enable_chip(rs, false); - rs->type = SSI_MOTO_SPI; rs->master = master; rs->dev = &pdev->dev; rs->max_freq = clk_get_rate(rs->spiclk);