[3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v2)
diff mbox series

Message ID 20181107222805.96638-3-bob.j.paauwe@intel.com
State New
Headers show
Series
  • [1/3] drm/i915: Make 48bit full ppgtt configuration generic (v8)
Related show

Commit Message

Bob Paauwe Nov. 7, 2018, 10:28 p.m. UTC
With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and the device info ppgtt field.

Aliasing PPGTT used by GEN 6 is a bit of an exception.  For those cases,
it makes just as much sense to check if we're running on GEN 6 as it
does to check a device info flag.

v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c                 | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h                 | 8 +++++---
 drivers/gpu/drm/i915/i915_gem_context.c         | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c             | 2 +-
 drivers/gpu/drm/i915/i915_pci.c                 | 6 ------
 drivers/gpu/drm/i915/intel_device_info.c        | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h        | 9 +--------
 drivers/gpu/drm/i915/selftests/huge_pages.c     | 4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   | 2 +-
 10 files changed, 19 insertions(+), 25 deletions(-)

Comments

kbuild test robot Nov. 8, 2018, 12:21 p.m. UTC | #1
Hi Bob,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20181107]
[cannot apply to v4.20-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-Make-48bit-full-ppgtt-configuration-generic-v9/20181108-104436
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gvt/vgpu.c:47:50: error: undefined identifier 'VGT_CAPS_4LVL_PPGTT'
   drivers/gpu/drm/i915/gvt/vgpu.c: In function 'populate_pvinfo_page':
   drivers/gpu/drm/i915/gvt/vgpu.c:47:43: error: 'VGT_CAPS_4LVL_PPGTT' undeclared (first use in this function); did you mean 'VGT_CAPS_FULL_PPGTT'?
     vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
                                              ^~~~~~~~~~~~~~~~~~~
                                              VGT_CAPS_FULL_PPGTT
   drivers/gpu/drm/i915/gvt/vgpu.c:47:43: note: each undeclared identifier is reported only once for each function it appears in

vim +/VGT_CAPS_4LVL_PPGTT +47 drivers/gpu/drm/i915/gvt/vgpu.c

82d375d1 Zhi Wang    2016-07-05  37  
23736d1b Ping Gao    2016-10-26  38  void populate_pvinfo_page(struct intel_vgpu *vgpu)
82d375d1 Zhi Wang    2016-07-05  39  {
82d375d1 Zhi Wang    2016-07-05  40  	/* setup the ballooning information */
90551a12 Zhenyu Wang 2017-12-19  41  	vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
90551a12 Zhenyu Wang 2017-12-19  42  	vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
90551a12 Zhenyu Wang 2017-12-19  43  	vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
90551a12 Zhenyu Wang 2017-12-19  44  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
90551a12 Zhenyu Wang 2017-12-19  45  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
a2ae95af Weinan Li   2017-10-20  46  
a449bba0 Bob Paauwe  2018-11-07 @47  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
90551a12 Zhenyu Wang 2017-12-19  48  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
aa36ed6d Changbin Du 2018-05-15  49  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
a2ae95af Weinan Li   2017-10-20  50  
90551a12 Zhenyu Wang 2017-12-19  51  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
82d375d1 Zhi Wang    2016-07-05  52  		vgpu_aperture_gmadr_base(vgpu);
90551a12 Zhenyu Wang 2017-12-19  53  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
82d375d1 Zhi Wang    2016-07-05  54  		vgpu_aperture_sz(vgpu);
90551a12 Zhenyu Wang 2017-12-19  55  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
82d375d1 Zhi Wang    2016-07-05  56  		vgpu_hidden_gmadr_base(vgpu);
90551a12 Zhenyu Wang 2017-12-19  57  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
82d375d1 Zhi Wang    2016-07-05  58  		vgpu_hidden_sz(vgpu);
82d375d1 Zhi Wang    2016-07-05  59  
90551a12 Zhenyu Wang 2017-12-19  60  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
82d375d1 Zhi Wang    2016-07-05  61  
1c6ccad8 Tina Zhang  2018-05-14  62  	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
1c6ccad8 Tina Zhang  2018-05-14  63  	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
1c6ccad8 Tina Zhang  2018-05-14  64  
82d375d1 Zhi Wang    2016-07-05  65  	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
82d375d1 Zhi Wang    2016-07-05  66  	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
82d375d1 Zhi Wang    2016-07-05  67  		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  68  	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
82d375d1 Zhi Wang    2016-07-05  69  		vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  70  	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  71  
82d375d1 Zhi Wang    2016-07-05  72  	WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
82d375d1 Zhi Wang    2016-07-05  73  }
82d375d1 Zhi Wang    2016-07-05  74  

:::::: The code at line 47 was first introduced by commit
:::::: a449bba075f4efa6186f8c3930a11100d0185740 drm/i915: Make 48bit full ppgtt configuration generic (v9)

:::::: TO: Bob Paauwe <bob.j.paauwe@intel.com>
:::::: CC: 0day robot <lkp@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 05fe8e2852bd..b957677fbbf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@  static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+		if (INTEL_GEN(dev_priv) < 6)
+			value = I915_GEM_PPGTT_NONE;
+		else if (IS_GEN6(dev_priv))
+			value = I915_GEM_PPGTT_ALIASING;
+		else
+			value = I915_GEM_PPGTT_FULL;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ee0d3a283e9..950b0f50ee4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@  intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
 #define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+	(INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
 #define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+	(INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@  i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (HAS_FULL_PPGTT(dev_priv)) {
+	if (INTEL_GEN(dev_priv) > 6) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b4d5f28474a2..76bb88c8fe6d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2877,7 +2877,7 @@  int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+	if (IS_GEN6(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6e76635c970..816b41674e01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -249,7 +249,6 @@  static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_ALIASING, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -295,7 +294,6 @@  static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -349,7 +347,6 @@  static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -397,7 +394,6 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -442,7 +438,6 @@  static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
@@ -519,7 +514,6 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d002f54269af..25138654ff99 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -857,7 +857,7 @@  void intel_device_info_runtime_init(struct intel_device_info *info)
 
 	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 		DRM_INFO("Disabling ppGTT for VT-d support\n");
-		info->ppgtt = INTEL_PPGTT_NONE;
+		info->ppgtt_bits = 0;
 	}
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4d45d5eab65d..5dfab991ca14 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,12 +76,6 @@  enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
-	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
-	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
-	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-};
-
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
@@ -159,7 +153,6 @@  struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
-	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
@@ -192,7 +185,7 @@  struct intel_device_info {
 		u16 gamma_lut_size;
 	} color;
 
-	/* Full PPGTT address range size */
+	/* PPGTT address range size in number of bits */
 	int ppgtt_bits;
 };
 
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index c49ace1a4685..dfee0a09efa9 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1710,8 +1710,8 @@  int i915_gem_huge_page_mock_selftests(void)
 	if (!dev_priv)
 		return -ENOMEM;
 
-	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
+	/* Pretend to be a device which supports the 63b PPGTT */
+	mkwrite_device_info(dev_priv)->ppgtt_bits = 63;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 4365979d8222..e63ee21c2317 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@  static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!HAS_FULL_PPGTT(i915))
+	if (INTEL_GEN(i915) <= 6)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 69fe86b30fbb..417f2dc705f3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@  static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!HAS_FULL_PPGTT(dev_priv))
+	if (INTEL_GEN(dev_priv) <= 6)
 		return 0;
 
 	file = mock_file(dev_priv);