[2/3] drm/i915: Remove HAS_4LVL_PPGTT
diff mbox series

Message ID 20181108215610.206943-2-bob.j.paauwe@intel.com
State New
Headers show
Series
  • [1/3] drm/i915: Make 48bit full ppgtt configuration generic (v10)
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Commit Message

Bob Paauwe Nov. 8, 2018, 9:56 p.m. UTC
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h             | 2 --
 drivers/gpu/drm/i915/i915_pci.c             | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.h    | 1 -
 drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
 4 files changed, 4 insertions(+), 7 deletions(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97649c5614c9..3ee0d3a283e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@  intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv)	\
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d9686bc22f68..f6e76635c970 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -397,7 +397,7 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -519,7 +519,7 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 78df4de37665..4d45d5eab65d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@  enum intel_ppgtt {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-	INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8cc8ed75f941..c49ace1a4685 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1450,7 +1450,7 @@  static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_4LVL_PPGTT(dev_priv)) {
+	if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
 		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1711,7 +1711,7 @@  int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));