| Message ID | 1541814256-23254-3-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add support for LPASS clock controller for SDM845 | expand |
Quoting Taniya Das (2018-11-09 17:44:16) > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index f133b7f..ba8ff99 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -3153,6 +3153,34 @@ enum { > }, > }; > > +static struct clk_branch gcc_lpass_q6_axi_clk = { > + .halt_reg = 0x47000, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x47000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_lpass_q6_axi_clk", > + .flags = CLK_IS_CRITICAL, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_lpass_sway_clk = { > + .halt_reg = 0x47008, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x47008, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_lpass_sway_clk", > + .flags = CLK_IS_CRITICAL, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct gdsc pcie_0_gdsc = { > .gdscr = 0x6b004, > .pd = { > @@ -3453,6 +3481,8 @@ enum { > [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, > [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, > [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, > + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, > + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, Sigh, more coordination with sdm845 mtp problems here due to the clks being protected by firmware. I guess I can just merge this and the mtp dts bits will land in Andy's tree during the same merge window? Or I may need to take the dts bits for this into clk tree so that the broken time is only between two commits. > }; > > static const struct qcom_reset_map gcc_sdm845_resets[] = { > diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c > new file mode 100644 > index 0000000..2ef7f2a > --- /dev/null > +++ b/drivers/clk/qcom/lpasscc-sdm845.c > @@ -0,0 +1,192 @@ [...] > + > +static const struct of_device_id lpass_cc_sdm845_match_table[] = { > + { .compatible = "qcom,sdm845-lpasscc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table); Move this down to the before the driver structure please. > + > +static int lpass_cc_sdm845_probe(struct platform_device *pdev) > +{ > + const struct qcom_cc_desc *desc; > + int ret; > + > + lpass_regmap_config.name = "cc"; > + desc = &lpass_cc_sdm845_desc; > + > + ret = lpass_clocks_sdm845_probe(pdev, 0, desc); > + if (ret) > + return ret; > + > + lpass_regmap_config.name = "qdsp6ss"; > + desc = &lpass_qdsp6ss_sdm845_desc; > + > + return lpass_clocks_sdm845_probe(pdev, 1, desc); > +} > + > +static struct platform_driver lpass_cc_sdm845_driver = { > + .probe = lpass_cc_sdm845_probe, > + .driver = { > + .name = "sdm845-lpasscc", > + .of_match_table = lpass_cc_sdm845_match_table, > + }, > +}; > + > +static int __init lpass_cc_sdm845_init(void) > +{ > + return platform_driver_register(&lpass_cc_sdm845_driver); > +} > +subsys_initcall(lpass_cc_sdm845_init); > + > +static void __exit lpass_cc_sdm845_exit(void) > +{ > + platform_driver_unregister(&lpass_cc_sdm845_driver); > +} > +module_exit(lpass_cc_sdm845_exit); > + > +MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION?
Hello Stephen, On 11/22/2018 12:37 AM, Stephen Boyd wrote: > Quoting Taniya Das (2018-11-09 17:44:16) >> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c >> index f133b7f..ba8ff99 100644 >> --- a/drivers/clk/qcom/gcc-sdm845.c >> +++ b/drivers/clk/qcom/gcc-sdm845.c >> @@ -3153,6 +3153,34 @@ enum { >> }, >> }; >> >> +static struct clk_branch gcc_lpass_q6_axi_clk = { >> + .halt_reg = 0x47000, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x47000, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_lpass_q6_axi_clk", >> + .flags = CLK_IS_CRITICAL, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch gcc_lpass_sway_clk = { >> + .halt_reg = 0x47008, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x47008, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_lpass_sway_clk", >> + .flags = CLK_IS_CRITICAL, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct gdsc pcie_0_gdsc = { >> .gdscr = 0x6b004, >> .pd = { >> @@ -3453,6 +3481,8 @@ enum { >> [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, >> [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, >> [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, >> + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, >> + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, > > Sigh, more coordination with sdm845 mtp problems here due to the > clks being protected by firmware. I guess I can just merge this and the > mtp dts bits will land in Andy's tree during the same merge window? Or I > may need to take the dts bits for this into clk tree so that the broken > time is only between two commits. > >> }; >> >> static const struct qcom_reset_map gcc_sdm845_resets[] = { >> diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c >> new file mode 100644 >> index 0000000..2ef7f2a >> --- /dev/null >> +++ b/drivers/clk/qcom/lpasscc-sdm845.c >> @@ -0,0 +1,192 @@ > [...] >> + >> +static const struct of_device_id lpass_cc_sdm845_match_table[] = { >> + { .compatible = "qcom,sdm845-lpasscc" }, >> + { } >> +}; >> +MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table); > > Move this down to the before the driver structure please. > Would do it in the next patch. >> + >> +static int lpass_cc_sdm845_probe(struct platform_device *pdev) >> +{ >> + const struct qcom_cc_desc *desc; >> + int ret; >> + >> + lpass_regmap_config.name = "cc"; >> + desc = &lpass_cc_sdm845_desc; >> + >> + ret = lpass_clocks_sdm845_probe(pdev, 0, desc); >> + if (ret) >> + return ret; >> + >> + lpass_regmap_config.name = "qdsp6ss"; >> + desc = &lpass_qdsp6ss_sdm845_desc; >> + >> + return lpass_clocks_sdm845_probe(pdev, 1, desc); >> +} >> + >> +static struct platform_driver lpass_cc_sdm845_driver = { >> + .probe = lpass_cc_sdm845_probe, >> + .driver = { >> + .name = "sdm845-lpasscc", >> + .of_match_table = lpass_cc_sdm845_match_table, >> + }, >> +}; >> + >> +static int __init lpass_cc_sdm845_init(void) >> +{ >> + return platform_driver_register(&lpass_cc_sdm845_driver); >> +} >> +subsys_initcall(lpass_cc_sdm845_init); >> + >> +static void __exit lpass_cc_sdm845_exit(void) >> +{ >> + platform_driver_unregister(&lpass_cc_sdm845_driver); >> +} >> +module_exit(lpass_cc_sdm845_exit); >> + >> +MODULE_LICENSE("GPL v2"); > > MODULE_DESCRIPTION? > Would add it in the next patch.
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a611531..23adc4c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -293,6 +293,15 @@ config SDM_DISPCC_845 Say Y if you want to support display devices and functionality such as splash screen. +config SDM_LPASSCC_845 + tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller" + depends on COMMON_CLK_QCOM + select SDM_GCC_845 + help + Support for the LPASS clock controller on SDM845 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 981882e..3d530b1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o +obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index f133b7f..ba8ff99 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -3153,6 +3153,34 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg = 0x47000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6_axi_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg = 0x47008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_sway_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .pd = { @@ -3453,6 +3481,8 @@ enum { [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, }; static const struct qcom_reset_map gcc_sdm845_resets[] = { diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c new file mode 100644 index 0000000..2ef7f2a --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sdm845.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,lpass-sdm845.h> + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" + +static struct clk_branch lpass_audio_wrapper_aon_clk = { + .halt_reg = 0x098, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_audio_wrapper_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbm_aon_clk = { + .halt_reg = 0x12000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x12000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbm_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_aon_clk = { + .halt_reg = 0x1f000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbs_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_core_clk = { + .halt_reg = 0x20, + /* CLK_OFF would not toggle until LPASS is not out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_xo_clk = { + .halt_reg = 0x38, + /* CLK_OFF would not toggle until LPASS is not out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x38, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_sleep_clk = { + .halt_reg = 0x3c, + /* CLK_OFF would not toggle until LPASS is not out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x3c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config lpass_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *lpass_cc_sdm845_clocks[] = { + [LPASS_AUDIO_WRAPPER_AON_CLK] = &lpass_audio_wrapper_aon_clk.clkr, + [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr, + [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_sdm845_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_sdm845_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks), +}; + +static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = { + [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr, + [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr, + [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = { + .config = &lpass_regmap_config, + .clks = lpass_qdsp6ss_sdm845_clocks, + .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), +}; + +static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index, + const struct qcom_cc_desc *desc) +{ + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, desc, regmap); +} + +static const struct of_device_id lpass_cc_sdm845_match_table[] = { + { .compatible = "qcom,sdm845-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table); + +static int lpass_cc_sdm845_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + lpass_regmap_config.name = "cc"; + desc = &lpass_cc_sdm845_desc; + + ret = lpass_clocks_sdm845_probe(pdev, 0, desc); + if (ret) + return ret; + + lpass_regmap_config.name = "qdsp6ss"; + desc = &lpass_qdsp6ss_sdm845_desc; + + return lpass_clocks_sdm845_probe(pdev, 1, desc); +} + +static struct platform_driver lpass_cc_sdm845_driver = { + .probe = lpass_cc_sdm845_probe, + .driver = { + .name = "sdm845-lpasscc", + .of_match_table = lpass_cc_sdm845_match_table, + }, +}; + +static int __init lpass_cc_sdm845_init(void) +{ + return platform_driver_register(&lpass_cc_sdm845_driver); +} +subsys_initcall(lpass_cc_sdm845_init); + +static void __exit lpass_cc_sdm845_exit(void) +{ + platform_driver_unregister(&lpass_cc_sdm845_driver); +} +module_exit(lpass_cc_sdm845_exit); + +MODULE_LICENSE("GPL v2");
Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. LPASS clocks present on the global clock controller would be registered with the clock framework based on the protected-clock flag. Also do not gate these clocks if they are left unused, as the lpass clocks require the global clock controller lpass clocks to be enabled before they are accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock access. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 30 ++++++ drivers/clk/qcom/lpasscc-sdm845.c | 192 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.