@@ -56,6 +56,7 @@
#include "i915_params.h"
#include "i915_reg.h"
+#include "i915_pvinfo.h"
#include "i915_utils.h"
#include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds {
struct i915_virtual_gpu {
bool active;
u32 caps;
+ u32 pv_caps;
};
/* used in computing the new watermarks state */
@@ -2853,6 +2855,11 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.active;
}
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO;
+}
+
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
enum pipe pipe);
void
@@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level) \
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
+
#endif
@@ -55,6 +55,18 @@ enum vgt_g2v_type {
#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
#define VGT_CAPS_HWSP_EMULATION BIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
+#define VGT_CAPS_PVMMIO BIT(5)
+
+/*
+ * define different levels of PVMMIO optimization
+ */
+enum pvmmio_levels {
+ PVMMIO_ELSP_SUBMIT = 0x1,
+ PVMMIO_PLANE_UPDATE = 0x2,
+ PVMMIO_PLANE_WM_UPDATE = 0x4,
+ PVMMIO_MASTER_IRQ = 0x8,
+ PVMMIO_PPGTT_UPDATE = 0x10,
+};
struct vgt_if {
u64 magic; /* VGT_MAGIC */
@@ -107,7 +119,9 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
- u32 rsv7[0x200 - 24]; /* pad to one page */
+ u32 pvmmio_caps;
+
+ u32 rsv7[0x200 - 25]; /* pad to one page */
} __packed;
#define vgtif_reg(x) \
@@ -62,6 +62,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
{
u64 magic;
u16 version_major;
+ u32 gvt_caps;
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
@@ -76,9 +77,27 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
}
dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
dev_priv->vgpu.active = true;
- DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+ if (!intel_vgpu_has_pvmmio(dev_priv)) {
+ DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+ return;
+ }
+
+ /* If guest wants to enable pvmmio, it needs to enable it explicitly
+ * through vgt_if interface, and then read back the enable state from
+ * gvt layer.
+ */
+ gvt_caps = __raw_i915_read32(dev_priv, vgtif_reg(pvmmio_caps));
+ dev_priv->vgpu.pv_caps &= gvt_caps;
+ __raw_i915_write32(dev_priv, vgtif_reg(pvmmio_caps),
+ dev_priv->vgpu.pv_caps);
+ if (!dev_priv->vgpu.pv_caps)
+ return;
+
+
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+ dev_priv->vgpu.pv_caps);
}
bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
both u32 pv_caps field and pvmmio_caps are used to control the different level pvmmio feature for MMIO emulation in both guest and GVT. These fields are default zero, no pvmmio feature enabled. it also adds VGT_CAPS_PVMMIO capability BIT for guest to check GVTg can support PV feature or not. v0: RFC, introudced enable_pvmmio module parameter. v1: addressed RFC comment to remove enable_pvmmio module parameter by pv capability check. v2: rebase v3: distinct pv caps from guest and host. renamed enable_pvmmio to pvmmio_caps which is used for host pv caps. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: He Min <min.he@intel.com> Cc: Jiang Fei <fei.jiang@intel.com> Cc: Gong Zhipeng <zhipeng.gong@intel.com> Cc: Yuan Hang <hang.yuan@intel.com> Cc: Zhiyuan Lv <zhiyuan.lv@intel.com> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++ drivers/gpu/drm/i915/i915_pvinfo.h | 16 +++++++++++++++- drivers/gpu/drm/i915/i915_vgpu.c | 23 +++++++++++++++++++++-- 3 files changed, 47 insertions(+), 3 deletions(-)