[v17,04/23] x86/msr: Add IA32_FEATURE_CONTROL.SGX_ENABLE definition
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Message ID 20181116010412.23967-5-jarkko.sakkinen@linux.intel.com
State New
Headers show
  • [v17,01/23] x86/sgx: Update MAINTAINERS
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Commit Message

Jarkko Sakkinen Nov. 16, 2018, 1:01 a.m. UTC
From: Sean Christopherson <sean.j.christopherson@intel.com>

Add a new IA32_FEATURE_CONTROL bit, SGX_ENABLE, which must be set in
order to execute SGX instructions, i.e. ENCL{S,U,V}.  The existence of
the bit is enumerated by CPUID as X86_FEATURE_SGX.  Like all other
flags in IA32_FEATURE_CONTROL, the MSR must be locked for SGX_ENABLE
to take effect.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
 arch/x86/include/asm/msr-index.h | 1 +
 1 file changed, 1 insertion(+)

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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 80f4a4f38c79..082890bff490 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -487,6 +487,7 @@ 
 #define FEATURE_CONTROL_LOCKED				(1<<0)
 #define FEATURE_CONTROL_LMCE				(1<<20)
 #define MSR_IA32_APICBASE		0x0000001b